; []===========================================================[] ; ; NOTICE: THIS PROGRAM BELONGS TO AWARD SOFTWARE INTERNATIONAL(R) ; INC. IT IS CONSIDERED A TRADE SECRET AND IS NOT TO BE ; DIVULGED OR USED BY PARTIES WHO HAVE NOT RECEIVED ; WRITTEN AUTHORIZATION FROM THE OWNER. ; ; []===========================================================[] ; ;---------------------------------------------------------------------------- ;Rev Date Name Description ;---------------------------------------------------------------------------- ;R17 04/30/99 RIC Add "No_EDO_Support" definition. ;R13B 04/26/99 RIC Add VCM(Virtual Channel SDRAM) Sizing Support. ;R13A 04/26/99 RIC Fixed that "VCM_Support" definition cause Register- ; SDRAM hang in C1h ;R16 04/20/99 RIC Add "OEM_POST_CODE_C1" definition. ;R15 04/14/99 RIC Add a CLK Delay(Set 69h[4]=1) in 133MHZ DARM CLK for ; DRAM stability. ;R14 04/13/99 RIC Fixed that CPUCLK 66MHz hang at POST C1h in 693A chip ; by setting DRAM CLK = 'HOST - 33' in BIOS SETUP. ;R13 04/06/99 RIC Add "VCM_Support" definition for Virtual Channel SDRAM ; type detection. ;R12A 04/02/99 RIC Remove no use code. ;R12 03/30/99 RIC Support Register SDRAM ;R11 03/11/99 RIC Set CAS Latency to 3T when system power on three times ; fail. ;R10 02/25/99 ADS Fixed Some customer selled bad SDRAM to user. ;R09 01/14/99 ADS Some single side SDRAMs' chips are put on RIGHT side ; (most on left side), then the memory type detects fail. ;R08 10/12/98 RIC Add "CAS_Latency_Auto" function. ;R07 10/01/98 RIC Add the function that SDRAM run saft timing when ; system power on three times fail. ;R06 09/15/98 RIC Fix that some SDRAM set CL fail in DIMM3/4. ;R05 09/15/98 RIC Fix 32MB SDRAM(13x9, Hitach 4Mx8) detection fail. ; (detect error to be 16MB[12x9]) ;R04 09/09/98 RIC Add DRAM Async Item. ;R03 09/08/98 RIC Fix that System wait in C1h for a long time when ; biger size DRAM pluged. ;R02 09/03/98 RIC Fix that HCT7.6 test fail in un-report memory. ;R01 08/25/98 RIC Add "Ct_Preset_In_Chipboot_Area" for V6.00 ;R00 08/10/98 RIC Initialization. ;=========================================================================== ; ; FOUR_DIMM_SUPPORT EQU 1 ; For Four DIMM Design. ; ; MAB_SUPPORT EQU 1 ; For MAA & MAB Design. ; ; CKE1 EQU 1 ; For CKE1 Design. ; ; Global_CKE EQU 1 ; For Global CKE Design. ; ; Percharge_Command_Use_6T EQU 1 ; For Long DRAM Line Design. ; ; ONEDRIVING EQU 1 ; For Only MAA Design. ; ; Sizing_Driving EQU 0xxh ; For Special Driving Request. ; ; FastPage_Support EQU 1 ; Support FastPage DRAM ; ; (This definition can't support Register SDRAM) ; ; VCM_Support EQU 1 ; Support FastPage DRAM ; ; (This definition can't support EDO DRAM) ; ; Reduce_1_CLK_For_RSDRAM EQU 1 ; Reduce one clock for Register SDRAM. ; ;=========================================================================== ; ; Debug in 80h(9Eh) I/O Port : ; ; Debug_DRAM_Type EQU 1 ; For Debug All DRAM Type Detection. ; Debug_DRAM_ECC EQU 1 ; For Debug DRAM ECC Detection. ; Debug_EDO_Type EQU 1 ; For Debug EDO DRAM Type Detection. ; Debug_Sizing_Buffer EQU 1 ; For Debug Buffer Area for DRAM Sizing. ; Debug_DRAM_Sizing EQU 1 ; For Debug DRAM Sizing. ; Debug_DRAM_Driving_Banks EQU 1 ; For Debug DRAM Drive Banks Detection. ; Debug_DRAM_Driving EQU 1 ; For Debug DRAM Driving Value. ; ;=========================================================================== ;-------------------------------; ; Define/Macro/Subroutine ; ;-------------------------------; ifdef ECC IFNDEF CompileForBootROM ECC_SUPPORT EQU 1 CMOS_VT_ECC_BIT EQU 02h CMOS_VT_ECC EQU 13h ENDIF; CompileForBootROM endif; ECC ifdef FOUR_DIMM_SUPPORT MAB_SUPPORT EQU 1 IFNDEF CKE1 Global_CKE EQU 1 ; For Global CKE Design. ENDIF; CKE1 endif; FOUR_DIMM_SUPPORT ifndef MAB_SUPPORT IFNDEF ONEDRIVING ONEDRIVING EQU 1 ; For Only MAA Design. ENDIF; ONEDRIVING endif; MAB_SUPPORT ifdef CompileForBootROM ;R07 ifndef No_SDRAM_Load_Default ;R07 No_SDRAM_Load_Default EQU 1 ;R07 endif; No_SDRAM_Load_Default ;R07 endif; CompileForBootROM ;R07 ; EDI Flag : ; bit7-0 : DRAM Type SDRAM_CL EQU 80000h ; bit 19 of EDI : 0(3T)/1(2T) Cycle Latency MPATTERN0 EQU 012345678h ; Pattern MPATTERN1 EQU 0FEDCBA98h ; Pattern BANKSUPPORT EQU 8 ; 8 Bank BITMAPLASTBANK EQU 10000000b ; 8 Bank REGLASTBANK EQU 057h ; 8 Bank LASTBANK EQU (BANKSUPPORT-1) ; 8 Bank SIZEPERBANK EQU 10000000h ; 256M ADDRLASTBANK EQU (LASTBANK*SIZEPERBANK) ; (8-1)*256 ifdef COMPRESS_CODE IFDEF CompileForExtROM GET_CT: GET_PCI: CONFIG_ADDR EQU 0cf8h mov eax, 80000000h mov ax,cx and al,NOT 03h ;32 bit access for PCI mov dx,CONFIG_ADDR ;index is 0cf8h out dx,eax mov dl,0fch ;start from 0cfch or dl, cl in al,dx ret SET_CT: SET_PCI: xchg ax,cx shl ecx,16 ;save value xchg ax,cx ;restore cx mov eax, 80000000h mov ax, cx and al,NOT 03h ;32 bit access for PCI mov dx,CONFIG_ADDR ;index is 0cf8h out dx,eax mov dl,0fch ;start from 0cfch or dl, cl mov eax,ecx shr eax,16 out dx,al ret Move_Codes: mov ds,si mov es,di xor si,si xor di,di cld rep movsw ret ELSE; CompileForExtROM extrn Get_Ct:Near extrn Set_Ct:Near ENDIF;CompileForExtROM ;---------------; ; GDT Table ; ;---------------; GDTR1: ; global descriptor table register dw 8*3 ; LIMIT dw offset DGROUP:GDT1 dw 0fh ; in 0F000h segment GDT1: ; null descriptor dw 0 ; limit dw 0 ; base db 0 ; hibase db 0 ; access db 0 ; hilimit db 0 ; msbase CODE1_DT: ; cs - prom code segment CODE1_INDEX = ((offset CODE1_DT - offset GDT1)/8) SHL 3 dw 0ffffh ; limit dw 0 ; base a15-a0 db 0fh ; hibase a23-a16, assume we have 64k prom db 9fh ; access db 0 ; hilimit db 0 ; msbase a31-a24 DATA1_DT: ; ds - first 64k segment DATA1_INDEX = ((OFFSET DATA1_DT - OFFSET GDT1)/8) SHL 3 dw 0ffffh ; limit dw 0 ; base data segment points to db 0 ; hibase ; 00000000 db 93h ; access db 08fh ; hilimit (4GB) db 0 ; msbase ;-------------------------------; ; TABLE for memory sizing ; ;-------------------------------; ;*******************************; ; Register Table Before Sizing ; ;*******************************; DRAM_Table_1: db 058h, 088h db 059h, 088h db 05ah, 020h db 05bh, 040h db 05ch, 060h db 05dh, 080h db 05eh, 0a0h db 05fh, 0c0h db 056h, 0e0h db 057h, 0ffh db 060h, 000h ifdef Percharge_Command_Use_6T db 064h, 0D4h db 065h, 0D4h db 066h, 0D4h db 067h, 0D4h else; Percharge_Command_Use_6T db 064h, 094h db 065h, 094h db 066h, 094h db 067h, 094h endif; Percharge_Command_Use_6T db 06bh, 000h ifdef Global_CKE db 06ch, 010h else; Global_CKE db 06ch, 000h endif; Global_CKE ifdef Sizing_Driving db 06Dh, Sizing_Driving else; Sizing_Driving IFDEF ONEDRIVING db 06dh, 0B1h ; Bit 7 : 1 => Disable MAB ELSE; ONEDRIVING db 06dh, 031h ; Enable MAA & MAB ENDIF;ONEDRIVING endif; Sizing_Driving db 06eh, 000h db 06fh, 0ffh DRAM_Table_1_End: ;*******************************; ; Register Table Before Driving ; ;*******************************; DRAM_Table_2: db 05ah db 05ch db 05eh db 056h db 0 DRAM_Table_2_End: ;***************; ; MA TABLE ; ;***************; MA_TABLE db 0bh ;wraparound address of 8 bit column address db 1bh ;another wraparound address of smallest dram size of 8 bit column address db 01h ;loop number db 01h ;smallest dram size : 8M db 16h ;wraparound address of 9 bit column address db 19h ;another wraparound address of smallest dram size of 9 bit column address db 02h ;loop number db 01h ;smallest dram size : 8M db 18h ;wraparound address of 10 column address db 17h ;another wraparound address of smallest dram size of 10 bit column address db 03h ;loop number db 01h ;smallest dram size : 8M db 1ah ;wraparound address of 11 column address db 19h ;another wraparound address of smallest dram size of 11 column address db 02h ;loop number db 04h ;smallest dram size : 32M db 1bh ;wraparound address of 12 column address db 00h ; db 01h ; db 10h ;smallest dram size : 128M SDRAM_TABLE db 0dh ;wraparound address of 16M-bit SDRAM db 19h ; db 02h ; db 01h ;smallest dram size : 8M ;R10 - strat ifdef Fixed_Dirty_SDRAM db 18h ;wraparound address of 64M-bit SDRAM db 00h ; db 02h ; db 02h ;smallest dram size : 16*2M endif; Fixed_Dirty_SDRAM ;R10 - end db 19h ;wraparound address of 64M-bit SDRAM db 00h ; db 02h ; db 04h ;smallest dram size : 32M OFF_SDRAM_TABLE = (OFFSET SDRAM_TABLE - OFFSET MA_TABLE) ifdef VCM_Support ;R13B - starts VCM_TABLE db 15h ;wraparound address of VCM 64M Bit (A21) db 00h ; db 01h ; db 08h ;smallest dram size : 64M ;MA Type : VCM 64M bit(0Bh) db 00h ;Wrap-around address: 0 db 00h ;DRAM size : 64 Mbyte db 01h ; db 08h ;smallest dram size : 64M ;MA Type : VCM 64M bit(0Dh) OFF_VCM_TABLE = (OFFSET VCM_TABLE - OFFSET MA_TABLE) ;636823_start endif; VCM_Support ;R13B - ends endif ;COMPRESS_CODE ;[]==============================================================[] ; ; CT_Memory_Presence: ; ; Size the amount of on-board memory and update chipset ; registers ; ; Saves: BP,SP ; Entry: None ; Exit: None ; Note : 1. No stack available ;[]==============================================================[] ALIGN 4 PUBLIC CT_MEMORY_PRESENCE CT_MEMORY_PRESENCE PROC NEAR cli shl esp, 16 ;save sp ;R16 - start ifdef OEM_POST_CODE_C1 ;read current output value of GPIOs mov dx, ACPI_Port + 4FH ;GPIO port ReadNextGPO: shl eax, 8 in al, dx ;read current value dec dl ;next port cmp dl, 4CH ;last GPIO port jae short ReadNextGPO and eax, NOT 073E7D00H ;mask GPO8,10,11,12,13,14,17 ;18,19,20,21,24,25,26 or eax, 00186500H ;output POST C1H ;Output output value of GPIOs mov dx, ACPI_Port + 4CH ;GPIO port WriteNextGPO: out dx, al ;output shr eax, 8 inc dl ;next port cmp dl, 4FH ;last GPIO port jbe short WriteNextGPO endif; OEM_POST_CODE_C1 ;R16 - end ifdef CompileForExtROM ;R01 IFDEF Ct_Preset_In_Chipboot_Area ;R01 jmp Ct_Decompress_Hook ;R01 Ct_Decompress_Hook_End: ;R01 ENDIF;Ct_Preset_In_Chipboot_Area ;R01 endif; CompileForExtROM ;R01 ;R07 - starts ifndef No_SDRAM_Load_Default IFNDEF SDRAM_Load_Default_CMOS mov al, 37h out 70h, al ; in al, 71h ; mov ah,al and ah, 03h ; cmp ah, 03h ; jnz short not_reset and al, not (03h) jmp short @f not_reset: add al, ((03h shr 1) and (03h)) @@: out 71h, al ELSE; SDRAM_Load_Default_CMOS mov al, SDRAM_Load_Default_CMOS out 70h, al ; in al, 71h ; mov ah,al and ah, SDRAM_Load_Default_Bit ; cmp ah, SDRAM_Load_Default_Bit ; jnz short not_reset and al, not (SDRAM_Load_Default_Bit) jmp short @f not_reset: add al, ((SDRAM_Load_Default_Bit shr 1) and (SDRAM_Load_Default_Bit)) @@: out 71h, al ENDIF; SDRAM_Load_Default_CMOS endif ;No_SDRAM_Load_Default ;R07 - ends xor edi, edi ; Clear Flag ;R11 - starts ;--------------------------------------; ; Check if CMOS set CAS Latency 2 or 3 ; ;--------------------------------------; mov al, SDRAM_CMOS out 70h, al in al, 71h ;SDRAM_CL_BIT = 40h test al, SDRAM_CL_BIT ;if cas latency = 2 je short _3_CL ; then edi[19] = 1 or edi, SDRAM_CL _3_CL: ifdef CAS_Latency_Auto IFNDEF CompileForBootROM test al,SDRAM_CMOS_BIT jz short CAS_Latency_Auto_end ;is auto jmp CAS_Latency_Auto_Program CAS_Latency_Auto_end: ENDIF; CompileForBootROM endif; CAS_Latency_Auto ;R11 - ends ;R04 - start ;---------------; ; DRAM Async ; ;---------------; ifndef No_Have_DRAM_Async_Item IFNDEF No_SDRAM_Load_Default ;R07 - starts ifdef OEM_Error_Special_Show2 ;R11 mov bl, OEM_Error_CMOS_Bits2 xor bl, bl ;R11 endif;OEM_Error_Special_Show2 IFNDEF SDRAM_Load_Default_CMOS mov al, 37h ; If Load SDRAM out 70h, al ; Default Value ? in al, 71h ; and al, 03h cmp al, ((03h shl 1) and (03h)) ;R11 jz short DRAM_Run_66CLK ; Yes, jmp jnz short Not_Slower_DRAM_Timing ;R11 No, jmp ELSE; SDRAM_Load_Default_CMOS mov al, SDRAM_Load_Default_CMOS ; If Load SDRAM out 70h, al ; Default Value ? in al, 71h ; and al, SDRAM_Load_Default_Bit cmp al, ((SDRAM_Load_Default_Bit shl 1) and (SDRAM_Load_Default_Bit)) ;R11 jz short DRAM_Run_66CLK ; Yes, jmp jnz short Not_Slower_DRAM_Timing ;R11 No, jmp ENDIF; SDRAM_Load_Default_CMOS ;-------------------------------; ; Slower Down DRAM Timing ; ;-------------------------------; ifdef OEM_Error_Special_Show2 ;R11 xor bl, bl mov bl, OEM_Error_CMOS_Bits2 ;R11 Set Warning Flag. endif;OEM_Error_Special_Show2 ENDIF; No_SDRAM_Load_Default ;R07 - ends and edi,not SDRAM_CL ;R11 Set 3 CAS Latency jmp short DRAM_Run_66CLK ;R11 Set HCLK - 33MHz Not_Slower_DRAM_Timing: IFDEF DRAM_Async_CMOS mov al,DRAM_Async_CMOS out 70h,al in al,71h test al,DRAM_Async_CMOS_Bit ELSE; DRAM_Async_CMOS mov al,40h out 70h,al in al,71h test al,20h ENDIF;DRAM_Async_CMOS jz DRAM_Run_Host_CLK DRAM_Run_66CLK: ;R07 mov cx, VT692 + 68h ;R14 Is CPUCLK 66MHz ? ROM_Call Get_Ct ;R14 test al, 03h ;R14 Yes : Set DRAM jz short DRAM_Run_Host_CLK ;R14 CLK=HostCLK mov cx, VT692 + 69h ROM_Call Get_Ct or al, 80h ROM_Call Set_Ct DRAM_Run_Host_CLK: IFNDEF No_SDRAM_Load_Default ;R07 - starts ifdef OEM_Error_Special_Show2 mov al,OEM_Error_CMOS2 out 70h,al in al,71h and al, not OEM_Error_CMOS_Bits2 or al,bl out 71h,al endif;OEM_Error_Special_Show2 ENDIF; No_SDRAM_Load_Default else; No_Have_DRAM_Async_Item IFNDEF No_SDRAM_Load_Default ifdef OEM_Error_Special_Show2 xor bl, bl endif;OEM_Error_Special_Show2 IFNDEF SDRAM_Load_Default_CMOS mov al, 37h out 70h, al ; Default Value ? in al, 71h ; and al, 03h cmp al, ((03h shl 1) and (03h)) ELSE; SDRAM_Load_Default_CMOS mov al, SDRAM_Load_Default_CMOS ; If Load SDRAM out 70h, al ; Default Value ? in al, 71h ; and al, SDRAM_Load_Default_Bit cmp al, ((SDRAM_Load_Default_Bit shl 1) and (SDRAM_Load_Default_Bit)) ENDIF; SDRAM_Load_Default_CMOS jnz short @f ; No, jmp ifdef OEM_Error_Special_Show2 mov bl, OEM_Error_CMOS_Bits2 endif;OEM_Error_Special_Show2 mov cx, VT692 + 69h ROM_Call Get_Ct or al, 80h ROM_Call Set_Ct @@: ifdef OEM_Error_Special_Show2 mov al,OEM_Error_CMOS2 out 70h,al in al,71h and al, not OEM_Error_CMOS_Bits2 or al,bl out 71h,al endif;OEM_Error_Special_Show2 ENDIF; No_SDRAM_Load_Default ;R07 - ends endif; No_Have_DRAM_Async_Item ;R04 - end ;R11 ;--------------------------------------; ;R11 ; Check if CMOS set CAS Latency 2 or 3 ; ;R11 ;--------------------------------------; ;R11 mov al, SDRAM_CMOS ;R11 out 70h, al ;R11 in al, 71h ;SDRAM_CL_BIT = 40h ;R11 test al, SDRAM_CL_BIT ;if cas latency = 2 ;R11 je short _3_CL ; then edi[19] = 1 ;R11 or edi, SDRAM_CL ;R11 _3_CL: ;R11 ifdef CAS_Latency_Auto ;R08 - starts ;R11 IFNDEF CompileForBootROM ;R11 test al,SDRAM_CMOS_BIT ;R11 jz short CAS_Latency_Auto_end ;is auto ;R11 jmp CAS_Latency_Auto_Program ;R11 CAS_Latency_Auto_end: ;R11 ENDIF; CompileForBootROM ;R11 endif; CAS_Latency_Auto ;R08 - ends ;----------------------------------------; ; Initialize register for DRAM detection ; ;----------------------------------------; mov si,offset DGROUP:DRAM_Table_1 Init_DRAM_Table_1_Loop: movzx cx,byte ptr cs:[si] mov al,cs:[si+1] ROM_Call Set_Ct add si,2 cmp si,offset DGROUP:DRAM_Table_1_End jne short Init_DRAM_Table_1_Loop ;R15 - starts ifndef No_133MHz_DARM_Extra_Delay mov cx, VT692+68h ; Get Host CLK ROM_Call Get_Ct ; and al, 03h ; mov bl,al mov cx, VT692+69h ; Get Host CLK ROM_Call Get_Ct ; mov ah,al and ah, 0C0h ; or bl,ah ; cmp bl,01000001b ;133MHz : 01000001b jz short Is_133MHz cmp bl,00000010b ;133MHz : 00000010b jz short Is_133MHz cmp bl,00000011b ;133MHz : 00000011b jz short Is_133MHz jmp short Not_133MHz Is_133MHz: or al, 10h ; Add 1 CLK Delay ROM_Call Set_Ct ; Not_133MHz: endif; No_133MHz_DARM_Extra_Delay ;R15 - ends ;---------------------------; ; Switch to proctected mode ; ;---------------------------; mov ax, cs mov ds, ax assume ds:DGROUP lgdt fword ptr GDTR1 ;=GDTR1[CHIPBOOT.ASM] so DS = F000 mov eax, cr0 ;=[cpu.EQU]protected mode=o1h or al, 1 ;enter protected mode mov cr0, eax FAR_JMP DGROUP:$+4, 08h ;clear prefetch, BIOS CS mov ax, DATA1_INDEX mov ds, ax ;DS=0000h ifndef VCM_Support ;R13 ifndef No_EDO_Support ;R17 ;-------------------------; ; Test if DRAM is EDO RAM ; ;-------------------------; mov cx, VT692+68h ; Enable EDO test mode mov al, 08h ; ROM_Call Set_Ct ; mov ch, 0 ; loop counter xor esi, esi ; test_type: ALIGN 4 mov ax, 0100h mov byte ptr ds:[esi], ah mov byte ptr ds:[esi+8], al cmp ah, byte ptr ds:[esi] jnz short Not_EDO mov ax, 00FFh mov byte ptr [esi], ah mov byte ptr [esi+8], al cmp ah, byte ptr ds:[esi] jnz short Not_EDO mov cl, ch ; Remember corresponding EDO bank and cl, 0Eh ; for RX60h in di mov al, 01 ; shl al, cl ; or di, ax ; Not_EDO: inc ch add esi, SIZEPERBANK cmp ch, LASTBANK jbe test_type mov cx, VT692+68h ; Disable EDO test mode. mov al, 00h ; ROM_Call Set_Ct ; endif; No_EDO_Support ;R17 endif; VCM_Support ;R13 ifdef Debug_EDO_Type mov ax,di out 80h,al endif; Debug_EDO_Type ;-------------------------; ; Test if DRAM is FP DRAM ; ;-------------------------; xor bx, bx ; bl=loop counter ; bh=1 if SDRAM II ; bh=2 if REG-SDRAM xor esi, esi test_type_10: ifdef FastPage_Support mov dword ptr ds:[esi], not 0a55a5aa5h mov dword ptr ds:[esi+8], 0a55a5aa5h jcxz short $+2 jcxz short $+2 jcxz short $+2 jcxz short $+2 cmp dword ptr ds:[esi], not 0a55a5aa5h jz next_sdram_bank ; FastPage => JMP! endif; FastPage_Support ;-----------------------; ; Test if DRAM is SDRAM ; ;-----------------------; ;R13 - starts ifdef VCM_Support cmp bh,04 jnz short Not_VCM_0 IFDEF PERFORMANCE ;R13B mov cx, VT692+68h ; Disable Bank Page Rom_Call Get_Ct ; and al, not 040h ; Rom_Call Set_Ct ; ENDIF;PERFORMANCE ;R13B mov cx, VT692 + 6bh ROM_Call Get_CT or al, 02h and al,not 01h ROM_Call Set_CT Not_VCM_0: endif; VCM_Support ;R13 - ends ;*******************************; ; Set SDRAM Timing of This Bank ; ;*******************************; mov ax, 0003h ;Set corresponding DRAM Bank to SDRAM type mov cl, bl and cl, 0feh shl al, cl ;If this bank is detected then bypass it test ax, di ; jnz next_sdram_bank ifdef SDRAM_II_EXIST cmp bh, 1 jne AAA mov al, 02h AAA: endif ;SDRAM_II_EXIST mov cx, VT692+60h ROM_Call Set_Ct ;R13 - starts ifdef VCM_Support cmp bh,04 jnz short Not_VCM_1 mov cx, VT692 + 58h test bl, 04h jz short @f inc cl @@: Rom_Call Get_Ct mov dl, 0d0h test bl, 02h jz @f shr dl, 04h @@: or al, dl ;if VCM, then column bit is 0dh Rom_Call Set_Ct Not_VCM_1: endif; VCM_Support ;R13 - ends mov al, bl shr al, 01 mov cx, VT692+64h add cl, al ROM_Call Get_Ct ifdef Have_Page_Mode_Item and al, NOT 3Bh else; Have_Page_Mode_Item and al, NOT 38h endif; Have_Page_Mode_Item ifdef SDRAM_II_EXIST ;R12A cmp bh, 01 ;if SDRAM_II je SET_SDRAM ; then RX6x[4,5]=01b endif; SDRAM_II_EXIST ;R12A cmp bh, 04 ;else if VCM ;R13 je _2_CL_ ; then RX6x[4,5]=01b ;R13 ;else test edi, SDRAM_CL ; if edi[19] = 1 jz short _3_CL_ ; then RX6x[5,4]=01b (2 CL) _2_CL_: ;R13 or al, 10h ; else jmp short SET_SDRAM ; RX6x[5,4]=10b (3 CL) _3_CL_: or al, 20h SET_SDRAM: ROM_Call Set_Ct ; Set SDRAM Timing of This Bank ;*******************************; ; SDRAM Initialize SEQUence ; Have 6 Step. ;*******************************; mov dword ptr ds:[esi], 0a55a5aa5h ; 1st > Write mov dword ptr ds:[esi+SIZEPERBANK], 0a55a5aa5h mov cx, VT692+6ch ; >> Step A: << ifdef Global_CKE ; mov al ,11h ; Set "NOP Command" else; Global_CKE ; /SDRAM Test Mode. mov al ,01h ; endif; Global_CKE ; ROM_Call Set_Ct ; ROM_Call IODELAY_100us ; Delay 100 us mov eax, dword ptr ds:[esi] ; 2nd > Read mov eax, dword ptr ds:[esi+SIZEPERBANK] ; (Dummy Read) mov cx, 010h ; Wait at least 200 us W_200U_Loop: ; ROM_Call IODELAY_100us ; loop short W_200U_Loop ; ifdef SDRAM_II_EXIST cmp bh, 01 jne short NOT_SDRAM_II mov al, 03h ;Issue a MRS command ROM_Call Set_Ct mov eax, dword ptr ds:[esi + 100] mov eax, dword ptr ds:[esi+10000100h] ; DLL reset mov cx, 0c8h ;200 clock cycle input W_200U_Loop_1: mov eax, dword ptr ds:[esi] mov eax, dword ptr ds:[esi+SIZEPERBANK] loop short W_200U_Loop_1 NOT_SDRAM_II: endif; SDRAM_II_EXIST mov cx, VT692+6ch ; >> Step B : << ifdef Global_CKE ; mov al ,12h ; Set "Precharge Command" else; Global_CKE ; /SDRAM Test Mode. mov al, 02h ; endif; Global_CKE ; ROM_Call Set_Ct ; mov eax, dword ptr ds:[esi] ; 3rd > Read mov eax, dword ptr ds:[esi+SIZEPERBANK] ; (Dummy Read) mov cx, VT692+6ch ; >> Step C : << ifdef Global_CKE ; mov al ,14h ; Set "CBR Cycle" else; Global_CKE ; /SDRAM Test Mode. mov al, 04h ; endif; Global_CKE ; ROM_Call Set_Ct ; ifdef SDRAM_II_EXIST cmp bh, 01 jne short NO_REFRESH mov cx, VT692+6ah mov al, 01h ROM_Call Set_Ct NO_REFRESH: endif; ifdef SDRAM_II_EXIST mov cx, 8 ; 8th read 0 and wait 100 us between reads Loop_8_: mov eax, dword ptr ds:[esi] ; 4th > Read 8th mov eax, dword ptr ds:[esi+SIZEPERBANK] ROM_Call IODELAY_100us loop short Loop_8_ mov cx, VT692+6ch ; >> Step D : << ifdef Global_CKE ; mov al ,13h ; Set "MSR" else; Global_CKE ; /SDRAM Test Mode. mov al, 03h ; endif; Global_CKE ; ROM_Call Set_Ct ; ;********************************; ; Set SDRAM Cycle Latency ; >> Step E : << ;********************************; ;R13 - starts ifdef VCM_Support cmp bh,04 jnz Not_VCM_2 ; MRS Command ; mov eax, ds:[esi+1a8h] ;SCLR mov eax, ds:[esi+00000310h] ;Chan. 0 SCCR mov eax, ds:[esi+04000310h] ;Chan. 1 SCCR mov eax, ds:[esi+00000350h] ;Chan. 2 SCCR mov eax, ds:[esi+04000350h] ;Chan. 3 SCCR mov eax, ds:[esi+01000310h] ;Chan. 4 SCCR mov eax, ds:[esi+05000310h] ;Chan. 5 SCCR mov eax, ds:[esi+01000350h] ;Chan. 6 SCCR mov eax, ds:[esi+05000350h] ;Chan. 7 SCCR mov eax, ds:[esi+00002310h] ;Chan. 8 SCCR mov eax, ds:[esi+04002310h] ;Chan. 9 SCCR mov eax, ds:[esi+00002350h] ;Chan. 10 SCCR mov eax, ds:[esi+04002350h] ;Chan. 11 SCCR mov eax, ds:[esi+01002310h] ;Chan. 12 SCCR mov eax, ds:[esi+05002310h] ;Chan. 13 SCCR mov eax, ds:[esi+01002350h] ;Chan. 14 SCCR mov eax, ds:[esi+05002350h] ;Chan. 15 SCCR jmp short sdram_normal Not_VCM_2: endif; VCM_Support ;R13 - ends ifdef SDRAM_II_EXIST cmp bh, 01 jne short SET_SDRAM_CL test edi, SDRAM_CL je short SDRAM_II_3CL mov eax, ds:[esi+120h] mov eax, ds:[esi+120h+SIZEPERBANK] jmp sdram_normal SDRAM_II_3CL: mov eax, ds:[esi+130h] mov eax, ds:[esi+130h+SIZEPERBANK] jmp sdram_normal SET_SDRAM_CL: endif; SDRAM_II_EXIST test edi, SDRAM_CL je SDRAM_3CL IFNDEF ONEDRIVING cmp bl, 03h ; jbe short Bank0123 ; ;R06 mov eax, ds:[esi+60006a8h] ; Special For ;R06 mov eax, ds:[esi+60006a8h+SIZEPERBANK] ; Bank4567 mov eax, ds:[esi+60036a8h] ;R06 Special For mov eax, ds:[esi+60036a8h+SIZEPERBANK] ;R06 Bank4567 jmp sdram_normal ; MAB Design Bank0123: ; ENDIF; ONEDRIVING mov eax, ds:[esi+150h] mov eax, ds:[esi+150h+SIZEPERBANK] jmp sdram_normal SDRAM_3CL: IFNDEF ONEDRIVING cmp bl, 03h ; jbe short Bank0123_ ; ;R06 mov eax, ds:[esi+6000628h] ; Special For ;R06 mov eax, ds:[esi+6000628h+SIZEPERBANK] ; 692 Bank4567 mov eax, ds:[esi+6003628h] ;R06 Special For mov eax, ds:[esi+6003628h+SIZEPERBANK] ;R06 692 Bank4567 jmp sdram_normal ; MAB Design Bank0123_: ; ENDIF; ONEDRIVING ;; 3CL + Burst Write mov eax, ds:[esi+1d0h] mov eax, ds:[esi+1d0h+SIZEPERBANK] sdram_normal: mov cx, VT692+6ch ; >> Step F : << ifdef Global_CKE ; mov al ,10h ; Set Normal SDRAM Mode. else; Global_CKE ; mov al, 0 ; endif; Global_CKE ; ROM_Call Set_Ct ; ;R13 - starts ifdef VCM_Support cmp bh,04 jnz short Not_VCM_3 mov cx, VT692+6bh ; Enable ROM_Call Get_CT or al, 01h ROM_Call Set_CT IFDEF PERFORMANCE ;R13B mov cx, VT692+68h ROM_Call Get_CT or al, 40h ROM_Call Set_CT ENDIF;PERFORMANCE ;R13B Not_VCM_3: endif; VCM_Support ;R13 - ends ;***************************************; ; If This Bank DRAM Is SDRAM ? ; ;***************************************; test_sdram: mov dword ptr ds:[esi], not 0a55a5aa5h mov dword ptr ds:[esi+8], 0a55a5aa5h jcxz short $+2 jcxz short $+2 jcxz short $+2 jcxz short $+2 cmp dword ptr ds:[esi], not 0a55a5aa5h ifndef ECC_SUPPORT ;R09 - starts ;;Question: Some single side SDRAMs' chips are put on RIGHT side (most on left ;; side), then the memory type detects fail. ;;Solution: The original algorithm about SDRAM detection only detects bank 0, ;; 2, 4, and 6. It assumes that if bank N is empty, then bank N+1 ;; must be empty. N=0,2,4,6. In other words, we can say it must be ;; fail in the general case: bank N is none, but bank N+1 exists. N= ;; 0,2,4,6. Hance, I just add the next bank checking (ie., bank N+1) ;; to solve this problem. Please search the string: ;; special_for_right_side_sdram ifdef special_for_right_side_sdram jz _sdram_left_exist mov dword ptr ds:[esi+SIZEPERBANK], not 05aa5aa5ah mov dword ptr ds:[esi+8+SIZEPERBANK], 05aa5aa5ah jcxz short $+2 jcxz short $+2 jcxz short $+2 jcxz short $+2 cmp dword ptr ds:[esi+SIZEPERBANK], not 05aa5aa5ah endif; special_for_right_side_sdram jnz next_sdram_bank _sdram_left_exist: ;;R09 ;R09 - ends else; ECC_SUPPORT jz short got_sdram mov eax, dword ptr ds:[esi] ; Test => xor eax, not 0a55a5aa5h ; If only one bit different ? clc ; (ECC admit one bit error.) Search_Error_Bit: ; sar eax, 1 ; jnc short Search_Error_Bit ; ;R09 - starts ifdef special_for_right_side_sdram jz short got_sdram ;;only one bit error ;;check next bank mov dword ptr ds:[esi+SIZEPERBANK], not 05aa5aa5ah mov dword ptr ds:[esi+8+SIZEPERBANK], 05aa5aa5ah jcxz short $+2 jcxz short $+2 jcxz short $+2 jcxz short $+2 cmp dword ptr ds:[esi+SIZEPERBANK], not 05aa5aa5ah jz short got_sdram mov eax, dword ptr ds:[esi+SIZEPERBANK] xor eax, not 05aa5aa5ah clc No_Find_Error_Bit: sar eax, 1 jnc short No_Find_Error_Bit endif; special_for_right_side_sdram ;R09 - ends jnz SDRAM_II ; got_sdram: endif; ECC_SUPPORT mov ax, 03h ; Set corresponding DRAM Bank ifdef SDRAM_II_EXIST ; to SDRAM type. cmp bh, 01 ; jne DRAM_TYPE ; mov ax, 02h ; DRAM_TYPE: ; endif; SDRAM_II_EXIST ; mov cl, bl ; and cl, NOT 01h ; shl al, cl ; or di, ax ; SDRAM_II: ifdef SDRAM_II_EXIST ; Set SDRAM II type detection cmp bh, 01h ; je next_sdram_bank ; mov bh, 01h ; jmp test_type_10 ; endif; SDRAM_II_EXIST ; next_sdram_bank: ifdef SDRAM_II_EXIST ;R12A xor bh, bh endif; SDRAM_II_EXIST ;R12A inc bl inc bl add esi, SIZEPERBANK+SIZEPERBANK cmp bl, LASTBANK jbe test_type_10 ;R13A ;R13 - starts ;R13A ifdef VCM_Support ;R13A cmp bh,04 ; Have detected VCM SDRAM ? ;R13A jz short Virtual_Channel_DRAM_End ; Yes, jmp ! ;R13A ;R13A mov bx,0400h ; Detect VCM DRAM ;R13A xor esi, esi ; ;R13A jmp test_type_10 ; ;R13A ;R13A Virtual_Channel_DRAM_End: ;R13A endif; VCM_Support ;R13A ;R13 - ends ;R12 - start ifndef FastPage_Support ;***************************************; ; Register SDRAM Detection ; ;***************************************; ;R12A cmp bh, 02h ; Have detected Register SDRAM ? ;R12A je short Register_DRAM_End ; Yes, jmp ! cmp bh, 02h ; Have detected Register SDRAM ? ;R13A je short Test_RSDRAM_Func ; Yes, jmp ! ;R13A test di,0ffh ; Have other Type DRAM ? jnz short Register_DRAM_End ; Yes, jmp ! mov bx, 0200h ; Detect Register SDRAM. xor esi, esi ; mov cx, VT692 + 69h ; ROM_Call Get_CT ; or al, 02h ; ifdef Reduce_1_CLK_For_RSDRAM ;R13A and al, 0efh ; Reduce 1 Clock endif; Reduce_1_CLK_For_RSDRAM ;R13A ROM_Call Set_CT ; jmp test_type_10 ; Test_RSDRAM_Func: ;R13A - starts test di,0ffh ; Have Register SDRAM ? jnz short Register_DRAM_End ; Yes, jmp ! mov cx, VT692 + 69h ; Disbale Register SDRAM ROM_Call Get_CT ; and al,not 02h ; ROM_Call Set_CT ;R13A - ends Register_DRAM_End: endif; FastPage_Support ;R12 - end ;R13A - starts ifdef VCM_Support ;***************************************; ; Virtual Channel SDRAM Detection ; ;***************************************; mov cx,VT692 + 08h ; North Bridge Reversion ID ROM_call Get_Ct ; cmp al, 40h ; If 693A chip ? jb short Virtual_Channel_DRAM_End ; No, jmp ! cmp bh,04 ; Have detected VCM SDRAM ? jz short Virtual_Channel_DRAM_End ; Yes, jmp ! mov bx,0400h ; Detect VCM DRAM xor esi, esi ; jmp test_type_10 ; Virtual_Channel_DRAM_End: endif; VCM_Support ;R13A - ends ;***********************************************; ; Type Test Over, Set RX60 Register From DI ; ;***********************************************; mov cx, VT692 + 60h ; Set DRAM type mov ax, di ; ROM_Call Set_Ct ; ifdef Debug_DRAM_Type out 80h,al endif; Debug_DRAM_Type ;-----------------------; ; ECC Initialization ; ;-----------------------; ifdef ECC_SUPPORT xor edi, edi mov ax, ds mov es, ax mov al, CMOS_VT_ECC ; If ECC set Enable ? out 70h, al ; in al, 71h ; test al, CMOS_VT_ECC_BIT ; IFDEF PARITY_SUPPORT mov al, 0fh jz short Parity_Only ELSE; PARITY_SUPPORT jz Not_ECC_0 ; No, Jmp ! ENDIF;PARITY_SUPPORT mov al, 8fh Parity_Only: mov cx, VT692+6eh ROM_Call Set_Ct xor esi, esi xor bx, bx parity_0_0: xor eax, eax mov ecx, 1000h mov edi, esi db 66h, 67h rep stosd mov cx, VT692+6fh ; Clear Status mov al, 0ffh ; ROM_Call Set_Ct ; mov ecx, 1000h ; Write xor eax, eax ; Loop_For_Write: ; mov dword ptr [esi], eax ; inc esi ; inc eax ; loop short Loop_For_Write ; xor si, si ; Read mov ecx, 1000h ; Loop_For_Read: ; mov eax, dword ptr [esi] ; inc esi ; loop short Loop_For_Read ; mov cx, VT692+6fh ; Have Parity DRAM ? ROM_Call Get_Ct ; (in this bank) IFDEF PARITY_SUPPORT ; test al, 88h ; ELSE; PARITY_SUPPORT ; test al, 80h ; ENDIF;PARITY_SUPPORT ; ifndef special_for_right_side_sdram ;;R09 jnz parity_10_0 ; No, Jmp ! else; special_for_right_side_sdram ;;R09 jz _original_prg ;;R09 Yes, pass N+1 bank checking endif; special_for_right_side_sdram ;;R09 ;R09 - starts ifdef special_for_right_side_sdram xor si,si add esi, SIZEPERBANK ;;next bank xor eax, eax mov ecx, 1000h mov edi, esi db 66h, 67h rep stosd mov cx, VT692+6fh mov al, 0ffh ROM_Call Set_Ct mov ecx, 1000h xor eax, eax n_Loop_For_Write: mov dword ptr [esi], eax inc esi inc eax loop short n_Loop_For_Write xor si, si mov ecx, 1000h n_Loop_For_Read: mov eax, dword ptr [esi] inc esi loop short n_Loop_For_Read sub esi, SIZEPERBANK mov cx, VT692+6fh ROM_Call Get_Ct IFDEF PARITY_SUPPORT test al, 88h ELSE; PARITY_SUPPORT test al, 80h ENDIF;PARITY_SUPPORT jnz parity_10_0 _original_prg: endif; special_for_right_side_sdram ;R09 - ends mov cl, bl ; Yes => Set Flag shr cl, 1 ; mov al, 1 ; shl al, cl ; or bh, al ; BH = Flag(Have Parity Bank) ; bit 0 : bank0/1 ; bit 1 : bank2/3 ; bit 2 : bank4/5 ; bit 3 : bank6/7 parity_10_0: xor si, si ; Test Next Bank add esi, SIZEPERBANK+SIZEPERBANK ; add bl,2 ; cmp bl, LASTBANK ; jbe parity_0_0 ; set_ecc: mov cx, VT692+6fh ; Clear ECC Status mov al, 0ffh ; ROM_Call Set_Ct ; and bh, 0fh ; If No ECC DRAM test bh, 0fh ; =>Set ECC Disable jnz short Have_ECC_ ; xor bh, bh ; jmp short set_ecc_1 ; Have_ECC_: IFDEF PARITY_SUPPORT or bh, 10h mov al, CMOS_VT_ECC out 70h, al in al, 71h test al, CMOS_VT_ECC_BIT jz short set_ecc_1 and bh, NOT 10h ENDIF;PARITY_SUPPORT or bh, 0a0h ; Set ECC Enable set_ecc_1: ; mov al, bh ; mov cx, VT692+6eh ; ROM_Call Set_Ct ; ifdef Debug_DRAM_ECC out 80h,al endif; Debug_DRAM_ECC Not_ECC_0: endif; ECC_SUPPORT ;--------------------------; ; Initialize memory sizing ; ;--------------------------; mov ax, ds mov es, ax ; ES = DS mov esi, ADDRLASTBANK ; ESI = Bank 7 location 0's address ifndef ECC_SUPPORT mov bx, di ; bl: DRAM Type else; ECC_SUPPORT mov cx, VT692+60h ROM_Call Get_Ct mov bl, al endif; ECC_SUPPORT ifdef VCM_Support ;R13B - starts mov cx, VT692+58h ROM_Call Get_Ct mov bh,al inc cl ROM_Call Get_Ct mov ah,bh ; AX = bank01/23/45/67 MA Type mov cx,4 ; loop num = 4 Set_VCM_Flag: test ah,10h ;If VCM DRAM Pluged ? jz short Not_VCM_DRAM_ ; No, jmp! and bl,not 01h ; Not_VCM_DRAM_: rol ax,4 ror bl,2 loop short Set_VCM_Flag endif; VCM_Support ;R13B - ends mov ah, LASTBANK ; AH = last plugged bank mov bh, BITMAPLASTBANK ; BH = loop counter xor dx, dx ; DL = plugged bank bit map ;***************************************; ; Allocate 200 Byte Temperate Area ; ;***************************************; test_dram_exist: xor al, al mov cx, 200h ; Write to 200 Byte Find_200B_Area_Loop: ; mov [esi], al ; inc al ; inc si ; loop short Find_200B_Area_Loop ; xor si, si ; Read from 200 Byte mov cx, 200h ; xor al, al ; Find_200B_Area_Loop_1: ; cmp al, [esi] ; jnz short No_200B_DRAM ; inc si ; inc al ; loop short Find_200B_Area_Loop_1 ; or dl, bh ; Set flag as last plugged DRAM found mov edi, esi ; inc dh ; or ah, 80h ; No_200B_DRAM: xor si, si ; Next Bank ! sub esi, SIZEPERBANK ; test ah, 80h ; jnz short BBB ; dec ah ; BBB: ; shr bh, 1 ; cmp bh, 0 ; jnz short test_dram_exist ; ifdef Debug_Sizing_Buffer mov al,dl out 80h,al mov al,dh out 9eh,al endif; Debug_Sizing_Buffer ;-----------------------; ; Memory Sizing ; ;-----------------------; ;EDI = address of the least plugged DRAM bank ;DL = plugged DRAM bit map ;DH = the number of plugged DRAM bank ;BL = plugged DRAM type ;AH = Last plugged DRAM bank DRAM_DES_OFF EQU 0102h DRAM_SIZE_OFF EQU BANKSUPPORT DRAM_TYPE_OFF EQU (DRAM_SIZE_OFF+BANKSUPPORT) LAST_DRAM_OFF EQU (DRAM_TYPE_OFF+BANKSUPPORT) DRAM_COUNT_OFF EQU (LAST_DRAM_OFF+1) xor di, di ; Clear 200 Byte xor al, al ; mov cx, 200h ; rep stosb ; xor di, di mov [edi+DRAM_DES_OFF-2], word ptr 055aah add di, DRAM_DES_OFF ;EDI: pointer to DRAM type and ah, NOT 80h mov [edi+LAST_DRAM_OFF], ah mov [edi+DRAM_COUNT_OFF], dh shl bx, 8 ; shl dx, 8 ; xor esi, esi fill_dram: test si, 1 jnz short odd_bank shr bx, 2 shr bl, 6 ;BL = Bank Type mov [edi+esi], bl mov [edi+esi+1], bl odd_bank: shr dx, 1 shr dl, 7 mov [edi+esi+DRAM_SIZE_OFF], dl inc si cmp si, LASTBANK jbe short fill_dram ;*******************************; ; Write data to each bank ; ;*******************************; xor cx, cx ; Loop counter for each bank xor esi, esi ; start from bank 0 write_data: mov ds:[esi], byte ptr 055h add esi, SIZEPERBANK ; Next bank address inc cl cmp cl, LASTBANK jbe write_data ;*******************************; ; Test each dram bank size ; ;*******************************; xor cx, cx xor esi, esi dram_size: shl ecx, 16 mov dword ptr ds:[esi+8], MPATTERN1 mov dword ptr ds:[esi], MPATTERN0 ;Data to check wraparound address ifdef Debug_DRAM_Sizing_PATTERN mov eax,0 cmp dword ptr [esi + eax], MPATTERN0 jnz short PATTERN_f mov al,04h out 80h,al jmp $ PATTERN_f: mov al,78h out 80h,al jmp $ endif; Debug_DRAM_Sizing_PATTERN xor bx, bx cmp [edi+DRAM_SIZE_OFF], byte ptr 0 ;If this bank is not plugged jz next_dram_100 ; then jmp to next bank cmp [edi], byte ptr 02h ;If not SDRAM/SDRAM-II type jb short DRAM_MA ; then bx = location 0 of DRAM_MA table ifdef VCM_Support ;R13B - starts mov bx, OFF_VCM_TABLE ; else-if is VCM je short DRAM_MA ; then bx = offset between MA_TABLE and VCM_TABLE endif; VCM_Support ;R13B - ends mov bx, OFF_SDRAM_TABLE ; else bx = offset between MA_TABLE and SDRAM_TABLE DRAM_MA: mov eax, 1 mov edx, 1 mov cx, word ptr CS:MA_TABLE[bx] shl eax, cl ;eax = first wraparound address cmp cl, 0h ;R13B if cl = 0, jne short WRA_Not_0h ;R13B mov eax, 0h ;R13B WRA_Not_0h: ;R13B mov cl, ch shl edx, cl ;edx = second wraparound address cmp cl, 0h ;if cl = 0, jne short Found_ ; then no second wraparound address mov edx, 0h Found_: mov cx, word ptr CS:MA_TABLE[bx + 2] ;cl = loop counter, ch = dram size same_cas: add eax, edx ;combine two wraparound address cmp dword ptr [esi + eax], MPATTERN0 jz short next_dram_100 sub eax, edx shl edx, 2 ; get second wraparound address of next type dram cmp bx,OFF_SDRAM_TABLE ; If has 16M bit SDRAM jne short _16M_A ; then second wraparound address should be shifted more ;R05 shr edx, 01h ; mov edx, 5000000h ;R05 issue MA13 and MA9 for SDRAM(A26+A24) _16M_A: ; cmp bx,OFF_SDRAM_TABLE + 4 ; if has 64M bit SDRAM jne short _64M_A ; then second wraparound address should be shifted more shl eax, 01h ; _64M_A: shl ch, 1 ;DRAM size multiple 2 for next type dram dec cl cmp cl, 00h jne same_cas ifdef VCM_Support ;R13B cmp bx,OFF_VCM_TABLE + 4 ;R13B If last item in MA TABLE else; VCM_Support ;R13B cmp bx,OFF_SDRAM_TABLE + 4 ; If last item in MA TABLE endif; VCM_Support ;R13B je next_dram_100 ; Then must be 64M bit SDRAM, 128M byte size cmp dword ptr [esi + eax], MPATTERN0;last case of same CAS jz short next_dram_100 add bl, 04h ;bl + 4 to point next CAS type jmp short DRAM_MA ;compare next CAS type next_dram_100: ifdef Debug_DRAM_Sizing mov al,ch out 80h,al mov ax,cx ; delay for a monent xor cx,cx ; xyz: ; NEWIODELAY ; loop short xyz ; mov cx,ax ; mov al,0ffh out 80h,al mov ax,cx ; delay for a monent xor cx,cx ; xyz_: ; NEWIODELAY ; loop short xyz_ ; mov cx,ax ; endif; Debug_DRAM_Sizing mov dl, ch shr ecx, 16 add ch, dl mov [edi + DRAM_SIZE_OFF], ch ifdef VCM_Support ;R13B - starts cmp bl,OFF_VCM_TABLE ; If VCM table1 jb short Not_VCM_ ; MA type = B sub bl,OFF_VCM_TABLE ; If VCM table2 shr bl,1 ; MA type = D add bl,0bh ; jmp short CCC ; Not_VCM_: ; endif; VCM_Support ;R13B - ends shr bl, 01h ;use offset of MA_TABLE to decide the cmp [edi], byte ptr 03h ;number of culomn address bits jnz short CCC shl bl, 01h and bl, 0fh CCC: mov [edi + DRAM_TYPE_OFF], bl inc edi and esi, 0f0000000h add esi, SIZEPERBANK inc cl cmp cl, LASTBANK jbe dram_size ;*******************************; ; Programming DRAM type & size ; ;*******************************; mov di, DRAM_DES_OFF ; EDI pointer to DRAM table xor bx, bx ; EBX = [VT692+58h--5bh] mov ecx, 4 Get_DT_Loop: ; Get DRAM type mov ax, [edi+DRAM_TYPE_OFF] shl bx, 4 or al, ah or bl, al add edi, 2 loop short Get_DT_Loop xchg bl, bh mov di, DRAM_DES_OFF shl ebx, 16 mov bx, [edi+DRAM_SIZE_OFF] ror ebx, 16 mov ecx, [edi+DRAM_SIZE_OFF+2] ; mov si, [edi+DRAM_SIZE_OFF+6] mov eax, 80000058h ; Set Reg58h - 5Bh mov dx, 0cf8h ; (EBX) out dx, eax ; MA Map Type mov eax, ebx ; Bank 0/1 mov dl, 0fch ; out dx, eax ; mov eax, 8000005ch ; Set Reg5Ch - 5Fh mov dl, 0f8h ; (ECX) out dx, eax ; Bank 2/3 mov eax, ecx ; Bank 4/5 mov dl, 0fch ; out dx, eax ; mov eax, 80000054h ; Set Reg56h - 57h mov dl, 0f8h ; (SI) out dx, eax ; Bank 6/7 mov ax, si ; mov dl, 0feh ; out dx, ax ; ifdef Have_Page_Mode_Item mov bl, 0h mov al, 40h ;Page_mode_item is in 40h out 70h, al in al, 71h test al, 10h jnz Disable_Page_Mode mov cx, VT692+6bh ROM_Call Get_Ct or al, 01h ROM_Call Set_Ct mov bl, 01h ifdef PERFORMANCE mov bl, 02h mov cx, VT692+68h ROM_Call Get_Ct or al, 0c0h ROM_Call Set_Ct endif ;PERFORMANCE Disable_Page_Mode: mov cx, VT692+64h ROM_Call Get_Ct and al, not 03h or al, bl ROM_Call Set_Ct mov cx, VT692+65h ROM_Call Get_Ct and al, not 03h or al, bl ROM_Call Set_Ct mov cx, VT692+66h ROM_Call Get_Ct and al, not 03h or al, bl ROM_Call Set_Ct mov cx, VT692+67h ROM_Call Get_Ct and al, not 03h or al, bl ROM_Call Set_Ct End_Page_Mode: endif ;Have_Page_Mode_Item ifndef Have_Page_Mode_Item mov cx, VT692+6bh ROM_Call Get_Ct or al, 01h ROM_Call Set_Ct endif; Have_Page_Mode_Item ;********************************; ; Programming ISA DMA top memory ; ;********************************; mov cx, VT586+48h ROM_Call Get_Ct or al, 01h ROM_Call Set_Ct shr si,8 ; Si = Memory Size mov bx, si ;Programming shl bx, 3 cmp bx, 16 jbe short Not_Over_16M mov bl, 16 Not_Over_16M: dec bl shl bl, 4 mov cx, VT586+4fh ROM_Call Get_Ct or al, bl ROM_Call Set_Ct ifdef ECC_SUPPORT xor edi, edi mov ax, ds mov es, ax IFNDEF FastPage_Support ;R03 - starts xor bl,bl mov cx, VT692 + 60h ROM_Call Get_Ct mov cx,4 Test_Have_DRAM_: shl bl,1 test al,0C0h jz short No_Have_DRAM_ or bl,1 No_Have_DRAM_: shl al,2 loop Test_Have_DRAM_ ENDIF; FastPage_Support ;R03 - ends mov cx, VT692 + 6Eh ROM_Call Get_Ct IFNDEF FastPage_Support ;R03 and al, bl ;R03 ENDIF; FastPage_Support ;R03 test al,0Fh jz short Not_ECC movzx ecx, si shl ecx, 23 shr ecx, 2 mov eax, 80000060h ; Enable shadow mov dx, 0cf8h ; and Enable A/B0000 out dx, eax ; redirect to DRAM mov dl, 0fch ; in eax, dx ; or eax, 51555500h ; out dx, eax ; xor eax, eax xor edi, edi db 66h, 67h rep stosd in eax, dx ; Disable shadow and eax, NOT 51555500h ; out dx, eax ; mov cx, VT692+6fh ; Clear status mov al, 0ffh ; ROM_Call Set_Ct ; Not_ECC: endif; ECC_SUPPORT ;-----------------------; ; Go Back to Real Mode ; ;-----------------------; mov eax, cr0 and al, not 01h mov cr0, eax FAR_JMP DGROUP:$+4, 0F000h ; Flush CPU instruction queue ;---------------------------------------------------------------; ; Set DRAM Driving/Timing According to DRAM Number & Colck ; ;---------------------------------------------------------------; ;***************; ; Dram Driving ; ;***************; ;if # bank of Single Side <= 3 => Rx6D = 21 ;if # bank of Double Side = 1 => Rx6D = 21 ;if 4 double side => Rx6D = 57 ;else Rx6D = 37 xor bx, bx mov cl, 0 mov si,offset DGROUP:DRAM_Table_2 mov eax, 80000000h Detect_Banks: xor ax, ax mov al, byte ptr cs:[si] cmp al, 0 jz short Detect_Banks_Over mov ch, al and al, 0fch mov dx, 0cf8h out dx, eax mov dl, 0fch or dl, ch in ax, dx cmp al, cl je short DDD mov cl, ah inc bl ; BL = single side cmp ah, al jz short DDD dec bl inc bh ; BH = double side DRAM DDD: inc si jmp short Detect_Banks Detect_Banks_Over: ifdef Debug_DRAM_Driving_Banks mov al, bh out 9eh,al mov al, bl out 80h,al endif; Debug_DRAM_Driving_Banks mov al, 025h cmp bx, 03h ; single bank <= 3 : 25h jbe short Set_Driving cmp bx, 100h ; 1 double : 25h je short Set_Driving mov al, 47h cmp bh, 04h ; 4 double : 47h je short Set_Driving mov al, 27h ; else : 27h Set_Driving: ifdef ONEDRIVING or al, 80h endif; ONEDRIVING mov cx, VT692+6dh ROM_Call Set_Ct ifdef Debug_DRAM_Driving out 80h,al endif; Debug_DRAM_Driving ;***********************; ; Other Dram Timing Reg ; ;***********************; mov cx, VT692+68h ; Set EDO to X-222-3-222 ROM_Call Get_Ct ; (bit5 = 0: X-222-2-222) or al, 20h ; (bit5 = 1: X-222-3-222) ROM_Call Set_Ct ; and al, 01h ; Bit0 = 0 : 66MHz ; => Set R6c[6] = 0 ; Set R6A = 43h ; Set R52[6] = 0 ; Bit0 = 1 : 100MHz ; => Set R6c[6] = 1 ; Set R6A = 65h ; Set R52[6] = 1 mov ebx, 406540h ; 100MHz Timing cmp al, 01h jz short _Not_66MHz mov ebx, 4300h ; 66MHz Timing _Not_66MHz: mov cx, VT692+6ch ; Reg 6C[6] = 0 mean : ROM_Call Get_Ct ; Concurrent with Cache Hit or al, bl ; Detection(for 66MHz) ROM_Call Set_Ct ; Reg 6C[6] = 1 mean : ; After Cache Hit ; Detection(for 100MHz) shr ebx, 8 mov cx, VT692+6ah ; Set DRAM Refresh Counter mov al, bl ; ROM_Call Set_Ct ; mov cx, VT692+52h ROM_Call Get_Ct or al, bh ROM_Call Set_Ct ;-----------------------; ; The End !!! ; ;-----------------------; shr esp, 16 ;restore SP clc ret CT_MEMORY_PRESENCE ENDP ;R08 - starts ifdef CAS_Latency_Auto IFNDEF CompileForBootROM CAS_Latency_Auto_Program: ;Check byte18 SDRAM CAS Latency shl esi,16 xor ah, ah ;Pre-Set Status mov bl,0a0h Check_CAS_Start: mov al, 18 mov si,offset DGROUP:@F jmp I2CByteRead ;Read SDP of Bank? SDRAM @@: jc short Not_Support_CAS_2 ;If no SPD => Jmp! cmp bh,0FFh jz short Not_Support_CAS_2 ;If SPD is BAD => Jump! test bh,00000010b ;If support latency =2T jz short CAS_3 CAS_2: or ah, 01h ; Set Have CAS_2 Status jmp short Not_Support_CAS_2 CAS_3: or ah, 02h ; Set Have CAS_3 Status Not_Support_CAS_2: add bl,2 cmp bl,0a6h ;DRAM number jbe short Check_CAS_Start test ah, 02h ;If have CAS_3 SPD => Jump! jnz short Not_Set_CAS_2 test ah,01h ;If no have CAS_2 SDP => Jmp! jz short Not_Set_CAS_2 or edi, SDRAM_CL ;set CAS= 2T Not_Set_CAS_2: IFDEF Always_Set_CAS_3_In_CAS_Latency_Auto and edi,not SDRAM_CL ;set CAS= 3T ENDIF;Always_Set_CAS_3_In_CAS_Latency_Auto shr esi,16 jmp CAS_Latency_Auto_end ;Function : Read a I2C byte value ;Input : BL - I2C ID address,AL - byte index ;Output : BH - value return if carry cleared ; Fail - if carr set I2CByteRead: ;set index byte to read mov dx,SMBus_Port +03h out dx,al ;Index NEWIODELAY ;set I2C ID No. mov dl,04h mov al,bl ;E2PROM read cmd or al,01H ;bit 0=1 for I2C read out dx,al NEWIODELAY ;wait SMbus ready ROM_CALL Chk_SMBus_READY ;start I2C read operation mov dl,02h mov al,48h out dx,al ;read data NEWIODELAY ;wait for a while mov cx,100h @@: newiodelay loop short @B ;check status OK ? ROM_CALL Chk_SMBus_READY jc short I2CFaile ;SMBus Fail ;read data mov dl,05 ;data port in al,dx ;Data0 NEWIODELAY mov bh,al ;value return I2CFaile: jmp si Chk_SMBus_READY Proc near mov dx,SMBus_Port + 0 clc mov cx,0100h Chk_I2c_OK: in al,dx ;get status NEWIODELAY or al,al jz short Clear_final test al,04h jnz short SMBus_Err test al,01h ;busy ? jz short Not_Smbusy ror ecx,16 mov cx,1000h @@: loop short @B ror ecx,16 Not_Smbusy: out dx,al loop short Chk_I2c_OK SMBus_Err: out dx,al ;clear status NEWIODELAY in al,dx test al,04H ;device error ? jnz short SMBus_Err stc Clear_final: ret Chk_SMBus_READY endp ENDIF; CompileForBootROM endif; CAS_Latency_Auto ;R08 - ends ;[]==============================================================[] ; IODELAY_100us: ; Delay about 100 us ; ;Destroy: ECX High Word ;Input : None ;Output: None ;[Notes] ; Stack not available ;[]==============================================================[] align 4 IODELAY_100us Proc shl ecx, 16 mov cl, 16 ; Dummy Out for Delay delay_loop_: ; NEWIODELAY ; dec cl ; jnz short delay_loop_ ; shr ecx, 16 ret IODELAY_100us endp ifdef CompileForExtROM ;R01 IFDEF Ct_Preset_In_Chipboot_Area ;R01 include CHIPBOOT.INC ;R01 ENDIF;Ct_Preset_In_Chipboot_Area ;R01 endif; CompileForExtROM ;R01 ;[]==============================================================[] ; Ct_Early_Shadow_System_Bios: ; Shadowing system before memory testing to speedup POST. ; ;Saves: SP,BP ;Input : None ;Output: None ;[Notes] ; 1. This routine will shadow system BIOS in early stage ; of POST. ; 2. Stack not available ;[]==============================================================[] align 4 PUBLIC Ct_Early_Shadow_System_Bios Ct_Early_Shadow_System_Bios PROC NEAR ifdef COMPRESS_CODE mov cx,VT692 + 63h CALL Get_Ct and al,0fh or al,50h CALL Set_Ct push ds mov si,ds mov di,0e000h mov cx,8000h call Move_Codes pop ds mov si,ds add si,1000h mov di,0f000h mov cx,8000h call Move_Codes ;program chipset with write protect mov cx,VT692 + 63h CALL Get_Ct and al,0fh or al,0a0h CALL Set_Ct else ;COMPRESS_CODE shl esp,16 ;save SP ; always force shadowing system BIOS ; programming register to setup mode ; Shadowing system BIOS ; programming register to setup mode mov cx,VT692 + 63h ROM_Call Get_Ct and al,0cfh or al,10h ROM_Call Set_Ct ;copy system BIOS to RAM mov ax, 0f000H mov cx, 04000H ;64K in dwords xor si, si xor di, di mov ds,ax ;set source segment mov es,ax ;set destination segment cld ;clear direction rep movsd ; programming register to write protect mode mov cx,VT692 + 63h ROM_Call Get_Ct and al,0cfh or al,20h ROM_Call Set_Ct ;Early_shadow_exit: shr esp,16 ;restore SP endif ;COMPRESS_CODE clc ret Ct_Early_Shadow_System_Bios ENDP ifdef Flash_2M_support ;[]==============================================================[] ; ; Enable_Extra_1MBIOS_Hook: ; ; Enable extra 1M bits BIOS ROMCS decode for decompress driver ROM ; ; Entry: None ; Exit: CX = Extra BIOS segment (0C000h or 0E000h) ; ZF = 1 Must be enter protect mode for access extra BIOS data ; 0 Access extra BIOS could in real mode ; Note : 1. Stack available ; 2. Save all register except CX ; 3. Must be return far ;[]==============================================================[] align 4 Enable_Extra_1MBIOS_Hook: pusha mov cx,VT586 + 43h call Get_Ct or al,040h ; enable fff8000-fffdffffh call Set_Ct popa xor cl,cl ; should enter protect mode mov cx,0c000h ;return extra BIOS segment retf ;must be return far for awdflash.exe ;[]==============================================================[] ; ; Disable_Extra_1MBIOS_Hook: ; ; Disable extra 1M bits BIOS ROMCS decode for recover original BIOS ; decode ; ; Entry: None ; Exit: None ; Note : 1. Stack available ; 2. Save all register ; 3. Must be return far ;[]==============================================================[] align 4 Disable_Extra_1MBIOS_Hook: pusha mov cx,VT586 + 43h call Get_Ct ;R02 and al,0f0h and al,not 040h ;R02 Disable fff8000-fffdffffh call Set_Ct popa retf ;must be return far for awdflash.exe endif ;Flash_2M_support ifndef No_Support_PCI_VGA_in_Bootblock ifdef CompileForBootROM ifdef Bootblock_16K_Support align 4 Ct_Enable_C_Shadow proc near ; C-ROM shadow Control ; 61h bit7,6 -- CC000-CFFFF ; 61h bit5,4 -- C8000-CBFFF ; 61h bit3,2 -- C4000-C7FFF ; 61h bit1,0 -- C0000-C3FFF ; 00 - Read/Write Disable ; 01 - Write Enable ; 10 - Read Enable ; 11 - Read/Write Enable pusha mov cx,VT692 + 61h mov bx,0FF00h call GET_SET_CT popa ret Ct_Enable_C_Shadow endp endif ;Bootblock_16K_Support endif ;CompileForBootROM endif ;No_Support_PCI_VGA_in_Bootblock