; []===========================================================[] ; ; NOTICE: THIS PROGRAM BELONGS TO AWARD SOFTWARE INTERNATIONAL(R) ; INC. IT IS CONSIDERED A TRADE SECRET AND IS NOT TO BE ; DIVULGED OR USED BY PARTIES WHO HAVE NOT RECEIVED ; WRITTEN AUTHORIZATION FROM THE OWNER. ; ; []===========================================================[] ; ;---------------------------------------------------------------------------- ;Rev Date Name Description ;---------------------------------------------------------------------------- ;R38 04/29/99 RIC Fixed that DRAM Clock detect fail in 693A. ;R37 04/29/99 RIC Add VCM DRAM Timing support for "VCM_Support" definition. ;R36 04/14/99 RIC Add "Have_IO_Recovery_Item" definition. ;R35 04/13/99 RIC Disable CPU-AGP Post Write for AGP stability. ;R34 04/12/99 RIC Add "USB_MOUSE_SUPPORT" definition. ;R10B 03/25/99 RIC Modify the defailt of DRAM Clock to 'HostCLK - 33M' ; from HostCLK and Add "DRAM_Default_Run_Host_Clock" ; definition. ;R33 03/11/99 ADS Remove "LAN_Ctrl_BY_LID" . ;R32 03/10/99 RIC Add "DRAM_Async_Val_" lable for 693A DRAM Asynchronous. ;R31 03/10/99 RIC Add "CAS_Latency_Auto" definition. ;R25A 03/02/99 ADS Add "TV_OUT_ITEM_IN_IOFEAT" to move TV_OUT Item to ; IOFEAT. ;R30 02/05/99 RIC Add "Have_DMA_Line_Buffer_ROM_Item" definition. ;R29 02/05/99 RIC Enable PCS0 IO trap for new 686A chip. ;R28 02/02/99 ADS Move "WO_ITEM" to cfeature. ; Please define "MOV_WO_ITEM_TO_CFEATURE" ;R27 02/01/99 PHI Move sensor code to XGROUP. ; Please use define SENSOR_IN_XGROUP. ;R26 01/20/99 RIC Add "Blink_Suspend_LED_In_GPO0" definition for 686A. ;R25 01/05/99 ADS Add "Issue_Gemlight_TV_Out_Function" define for customer request. ;R24 01/04/99 ADS Add "Chassis_Intrasion_ITEM" define for customer request. ;R23 12/31/98 ADS Add "APC_Power_LED_ITEM" define for customer request. ;R22 12/21/98 RIC Add "USB2_Separate_Control" define. ;R21 12/21/98 RIC Enable I/O Recovery Time for 686/686A SouthBridge. ;R20 12/16/98 RIC Add Item for En/Disable Onchip Sound/Modem in VT686. ;R19 12/14/98 RAY Fixed compiler error for 4.6 BIOS ;R18 12/07/98 RIC Add ROMITEM for customer to optimize performance. ; If customer want high performance, please set 51[3,2] ; to 1. ;R17 12/03/98 RIC Modify default of USB controller to Enable for VT686A. ;R16A 12/02/98 ADS Let CMOS be changed. ;R16 11/19/98 RIC Add BiosCache_Item feature. ; and add VideoRom_Item for SEPARATE_P6_VIDEO_ITEM ;R15 11/04/98 RIC Add "Power_Type_Selectable" definition. ;R10A 11/01/98 RIC Add "DRAM_Default_Run_AGP_Clock" define for ; DRAM_Async_Item ;R14 10/21/98 RIC Fix that 'CHIPSET FEATURE' title over-write 'AWARD' ; title. ;R07B 10/20/98 RIC Move USB Item to Left of Chipset Feature and add ; "CFEATURE_NO_SPLIT" define ;R13 09/29/98 RIC Remove Device ID ROMITEM to match VIA new driver. ;R07A 09/23/98 RIC Add "CLKGEN_Item_In_Left" define. ;R12 09/15/98 RIC Change the default of DRAM Timing Item to SDRAM. ;R11 09/11/98 ADS Suppost VIA VXD driver limite. ;R10 09/09/98 RIC Add DRAM Async Item. ;R09 09/09/98 RIC Add UltraMode2_Set_Mode1_Status ROMITEM. ;R08 09/03/98 RIC Modify Host Bridge Register 0ACh values(request by VIA). ;R07 09/01/98 RIC Add "USB_Item_In_Left" define. ;R06 09/01/98 RIC Add "OEM1_GPO_CNTL" define. ; "OEM2_GPO_CNTL" ; "OEM3_GPO_CNTL" ;R05 08/25/98 RIC If define "FOUR_DIMM_SUPPORT" , hide fourth DIMM ; DRAM Timing Item. ;R04 08/25/98 RIC Add a ROMITEM to Enable AGP PCI Master Allowed Before ; CPU-to-PCI Post Write Buffer is not Flushed ; And remove no use code. ;R03 08/24/98 RIC Add "REQ_GNT_PAIR" definition for SB_LINK_SUPPORT. ;R02 08/24/98 RIC Open 6Dh bit6-4 for "Have_DRAM_Driving_ROMITEM" define. ;R01 08/22/98 RIC Modify SouthBridge func3 Class to 0600h. ; (Request by VIA, Fix HCT7.6 error in combination with ; VIA new Driver.) ;R00 08/17/98 RIC Initialization. PAGE 56,132 .286 ;---------------; ; Include ; ;---------------; include bios.cfg include bsetup.inc include common.mac include common.equ include setup.ext SENSOR_IN_CFEATURE = 1 ifdef Update_Sensor_in_CPUFEAT SENSOR_IN_CFEATURE = 0 endif; Update_Sensor_in_CPUFEAT if SENSOR_IN_CFEATURE include sensor.ext endif; SENSOR_IN_CFEATURE include cmos.equ ifdef SUPPORT_TRADITIONAL_CHINESE COMPILE_FOR_LANGUAGE_EXTRN EQU 1 include Ct_B5.STR endif ;SUPPORT_TRADITIONAL_CHINESE ; ifdef SUPPORT_SIMPLIFIED_CHINESE ; COMPILE_FOR_LANGUAGE_EXTRN EQU 1 ; include GB.STR ; endif ;SUPPORT_SIMPLIFIED_CHINESE ; ifdef SUPPORT_JAPANESE ;jjpp ; COMPILE_FOR_LANGUAGE_EXTRN EQU 1 ;jjpp ; include JP.STR ;jjpp ; endif ;SUPPORT_JAPANESE ;jjpp CLKCNTL_IN_CFEATURE = 1 ifdef Update_Clkcntl_in_CPUFEAT CLKCNTL_IN_CFEATURE = 0 endif; Update_Clkcntl_in_CPUFEAT ;-----------------------; ; External Subroutine ; ;-----------------------; extrn Post_call_proc:near extrn _Get_Ct:near extrn F000_GetItem_Value:near extrn GetItem_Value:near extrn F000_call_proc:near extrn XCALL_PROC:near extrn X_Get_Ct:near extrn X_Set_Ct:near extrn Ct_Quatify_100Mhz:near extrn X_If_693A:Near ;R38 extrn X_Measure_SDRAM_Speed:Near ;R38 ;-----------------------; ; External Item/Label ; ;-----------------------; Extrn Common_Startup_Str:Near Extrn Std_Help_Str:Near Extrn Ena_Str:Near Extrn Dis_Str:Near Extrn NullStr:Near DECLARE_MULTI_LANGUAGE ;macro to declare externals ;---------------; ; Public ; ;---------------; Public Chip_Feature_Special_Do Public Chip_Feature_Special_Show Public Chip_Feature_StartUp_Str Public Chip_Feature_Start Public Chip_Feature_End Public CHIP_STAT Public Cmos_Check_Sum public Rom_Table public EndRom_Table public Auto_String public EndAuto_Table Public Auto_CPU_386DX Public Auto_CPU_386SX Public Auto_CPU_386SL Public Auto_CPU_486DX Public Auto_CPU_486SX Public Auto_CPU_486SLC Public Auto_CPU_486DLC Public Auto_CPU_IBM386SLC Public Auto_CPU_P24T Public Auto_CPU_P24D Public Auto_CPU_486DX2 Public Auto_CPU_IBM486SLC2 Public Auto_CPU_486S Public Auto_CPU_486S2 Public Auto_CPU_586 public Auto_CPU_486SXS public Auto_CPU_486DXS public Auto_CPU_486DX2S public Auto_CPU_IBM486DLC3 Public Bank01_Dram_Timing_Val Public Bank01_Dram_Timing_Val_ Public Bank23_Dram_Timing_Val Public Bank23_Dram_Timing_Val_ Public Bank45_Dram_Timing_Val Public Bank45_Dram_Timing_Val_ Public Bank67_Dram_Timing_Val Public Bank67_Dram_Timing_Val_ EGROUP GROUP ECODE DGROUP GROUP FCODE FCODE SEGMENT DWORD PUBLIC 'CODE' ASSUME CS:DGROUP,DS:DGROUP DEFINE_ITEM MACRO MENU_NAME,GAP IFNB Yaxis = Yaxis + GAP ENDIF ;GAP IF Yaxis GE 23 Xaxis = 42 Yaxis = 4 ELSE ; Yaxis = Yaxis + 1 ENDIF ; IFNB PUBLIC MENU_NAME MENU_NAME: ENDIF ENDM ; Chipset Feature Page ------------------------------------------------ Start db '$ML$' ;Signature For Multi-Language Chip_Feature_Special_Do: dw Chip_Feature_Do_NO Chip_Feature_Do_NO EQU (($ - offset Chip_Feature_Special_Do)-2)/4 Chip_Feature_Special_Show: dw Chip_Feature_Show_NO ifndef USB_Item_Not_In_Cfeat ifdef VT586_USB ifdef USB_SUPPORT ifndef USB2_Separate_Control ;R22 - starts dw ONBD_USB_Item, offset Show_USB_Legacy endif; USB2_Separate_Control ;R22 - ends endif ;USB_SUPPORT endif ;VT586_USB endif; USB_Item_Not_In_Cfeat if SENSOR_IN_CFEATURE include sensor.shw endif; SENSOR_IN_CFEATURE ifdef Jumpless_Support JUMPLESS_FOR_CFEATURE_ASM = 3 include JUMPLESS.INC endif; Jumpless_Support Chip_Feature_Show_NO EQU (($ - offset Chip_Feature_Special_Show)-2)/4 Chip_Feature_StartUp_Str label near STRSHOW <,,,offset Common_Startup_Str> ;R14 POS <,29,2> POS <,29,1> ;R14 db 'CHIPSET FEATURES SETUP' db 0 ;--------------------------------------------------------------------------- ALIGN 4 Cmos_Check_Sum label near db 10H ;STD checksum start location db 2DH ;STD checksum end location db 2EH ;STD checkum low byte ;STD checkum high byte(2FH) ;Check sum for VT82C505 db 40H ;checksum start location db 7aH ;checksum end location db 7bH ;checkum low byte ;checkum high byte(7cH) db 0 ;end of checksum ;[]==============================================================[] ;Rom_Table: (POST 08h) ; This table will be program in POST_8S ; This table can be modified by user in using MODBIN.EXE ;[]==============================================================[] ALIGN 4 public Rom_Table public EndRom_Table Rom_Table label near ;----------------; ; VT692 Register ; ;----------------; ROMITEM <2,VT692 + 051H,00000110b,004h> ;[3]:1/*4 Level DARM Read Buffer ;R18 ;[2]:*1/4 Level DARM Write Buffer ;R18 ;R04 ROMITEM <2,VT692 + 00dH,11111111b,020h> ;[7-3]:Latency Timer XXXXXh * 8 PCI Clock. ROMITEM <2,VT692 + 070H,01010111b,040h> ;[6]:Dis/*En PCI Master to DRAM Post-Write ;[4]:*Dis/En PCI Master to DRAM Prefetch ;[2]:*Dis/En PCI Master Read Caching ;[1]:*Dis/En Delay Transaction ;[0]:*Dis/En 1 Wait State PCI Cycles ROMITEM <2,VT692 + 071H,01001110b,008h> ;[6]:*Dis/En PCI Byte Merge ;[3]:Dis/*En PCI Burst ;[2]:*Dis/En PCI Fast Back-to-Back Write ;[1]:*Dis/En Quick Frame Generation ROMITEM <2,VT692 + 072H,11111111b,06ch> ;PCI control ROMITEM <2,VT692 + 073H,00001101b,000h> ;[3]:*Dis/En Assert STOP after PCI Master Write Timeout ;[2]:*Dis/En Assert STOP# after PCI Master Read Timeout ;[0]:*Dis/En PCI Master Broken Timer ROMITEM <2,VT692 + 074H,10011000b,008h> ;[7]:*Dis/En PCI Master Read Prefetch ;[4]:*FIB/Metal ;[3]:Dis/*En PCI#1 delay transaction time out ROMITEM <2,VT692 + 075H,11001111b,080h> ;[7]:Dis/*En PCI Arbitration Mechanism ;[6]:*REQ/Frame based Arbitration Mode ;[3-0]:Disable PCI master bus time-out ;R08 ROMITEM <2,VT692 + 0acH,00000010b,002h> ;[1]: set dummy request. ROMITEM <2,VT692 + 0acH,01000010b,040h> ;R08 [1]: *Dis/En AGP Arbitration Parking ;R08 [6]: set 1. ifdef Have_DRAM_Driving_ROMITEM ;R02 ROMITEM <2,VT692 + 06dH,00001111b,00fh> ;[3-0]:Enable DRAM Driving ROMITEM <2,VT692 + 06dH,01111111b,037h> ;R02 [6-0]:Enable DRAM Driving endif; Have_DRAM_Driving_ROMITEM ;R13 ROMITEM <2,VT692 + 0FFH,11111111b,005h> ;Set Device ID ;R13 ROMITEM <2,VT692 + 0FEh,11111111b,097h> ;Set Device ID ;R13 ROMITEM <2,VT692 + 0FCh,00000001b,001h> ;Enable Device ID BackDoor ;-------------------; ; VT692_PP Register ; ;-------------------; ;R04 ROMITEM <2,VT692_PP + 040H,11100011b,0E0h> ;[7]:Dis/*En AGP P2P CPU-PCI #2 Post Write ;R35 ROMITEM <2,VT692_PP + 040H,11101011b,0E8h> ;[7]:Dis/*En AGP P2P CPU-PCI #2 Post Write ;R04 ROMITEM <2,VT692_PP + 040H,11101011b,068h> ;[7]:*Dis/En AGP P2P CPU-PCI #2 Post Write ;R35 ;[6]:Dis/*En AGP P2P CPU-PCI #2 Dynamic Burst ;[5]:Dis/*En AGP P2P CPU-PCI #2 One Wait State Burst Write ;[3]:Dis/*En AGP PCI Master Allowed Before CPU-to-PCI Post Write Buffer is not Flushed ;R04 ;[1]:*Dis/En AGP P2P PCI #2 Master Read Caching ;[0]:*Dis/En AGP P2P PCI #2 Delay Transaction ROMITEM <2,VT692_PP + 041H,11111111b,05ch> ;PCI control ROMITEM <2,VT692_PP + 042H,00010000b,010h> ;[4]:Dis/*En Extend PCI Dummy Request Cycle ;-----------------------; ; VT596 Register ; ;-----------------------; ifdef VT686 ;R21 ROMITEM <2,VT686 + 040H,00001000b,008h> ;R21 [3]:Dis/*En I/O Recovery Time endif; VT686 ;R21 ifdef Have_Double_DMA_Clock_ROM_Item ROMITEM <2,VT586 + 041H,00001000b,000h> ;[3]:*Dis/En Double DMA Clock endif; Have_Double_DMA_Clock_ROM_Item ROMITEM <2,VT586 + 045H,10000000b,080h> ;[7]:Dis/*En DMA to PCI line buffer (for system stable) ROMITEM <2,VT586 + 046H,11110000b,060h> ;[7]:*Dis/En PCI Master Write States ;[6-5]:Enable flush line buffer for interrupt or DMA IOR cycle(to Solve 45[7] bug) ;[4]:Dis/*En Reg04 R/W ROMITEM <2,VT586 + 047H,01000000b,000h> ;[6]:*Dis/En PCI Delay Transaction ROMITEM <2,VT586 + 049H,00000001b,000h> ;[0]:Set 1 ROMITEM <2,VT586 + 04AH,10000000b,080h> ;[7]:Dis/*En Wait for Grant of IDE ifdef Route_By_MIRQ0 ROMITEM <2,VT586 + 055H,00Fh,Route_By_MIRQ0> ;MIRQ0 Routing endif; Route_By_MIRQ0 ifdef Route_By_MIRQ1 ROMITEM <2,VT586 + 057H,00Fh,Route_By_MIRQ1> ;MIRQ1 Routing endif; Route_By_MIRQ1 ifdef Have_DMA_Line_Buffer_ROM_Item ;R30 ROMITEM <2,VT586 + 05CH,00000001b,000h> ;R30 [0]:*Ena/Dis DMA Line Buffer endif; Have_DMA_Line_Buffer_ROM_Item ;R30 ;R04 ifdef VT596 ROMITEM <2,VT586 + 074H,00000001b,001h> ; Enable IOCHCK,LA[23-17] ; Fixed that boot from Floppy ;R04 endif; VT596 ROMITEM <2,VT586_IDE + 04H,11111111b,007h> ;[2-0]:Dis/*En PCI Bus of IDE ROMITEM <2,VT586_IDE + 05H,11111111b,000h> ;Clear Other Command Bit ifndef No_KeyLock_Function ROMITEM <2,VT586 + 059H,00000010b,02h> ;[1]:Dis/*En Key Lock endif; No_KeyLock_Function ROMITEM <2,VT586_ACPI + 063H,11111111b,006h> ; Bass Class Code (Reg0Bh) ;R01 ROMITEM <2,VT586_ACPI + 062H,11111111b,080h> ; Sub Class Code (Reg0Ah) ROMITEM <2,VT586_ACPI + 062H,11111111b,000h> ;R01 Sub Class Code (Reg0Ah) ;R03 - start ;-----------------------; ; PCI DMA Pair ; ;-----------------------; ifdef REQ_GNT_PAIR ROMITEM <2,VT596 + 07DH,(01h shl (REQ_GNT_PAIR-1)),> endif; REQ_GNT_PAIR ;R03 - ends ;-----------------------; ; PCS0/PCS1 control ; ;-----------------------; ifdef PCS0_Use_294h ifdef VT686 ;R29 ROMITEM <2,VT596 + 076H,00010010b,012h> ;R29 ROMITEM <2,VT596 + 077H,00000100b,004h> ;R29 Enable PCS0 IO Trap ROMITEM <2,VT596 + 078H,11111111b,094h> ;R29 ROMITEM <2,VT596 + 079H,11111111b,002h> ;R29 ROMITEM <2,VT596 + 080H,00001111b,003h> ;R29 else; VT686 ;R29 ROMITEM <2,VT596 + 076H,00010000b,010h> ROMITEM <2,VT596 + 078H,11111111b,094h> ROMITEM <2,VT596 + 079H,11111111b,002h> ROMITEM <2,VT596 + 080H,00001111b,003h> endif; VT686 ;R29 endif; PCS0_Use_294h ifdef PCS1_Use_294h ROMITEM <2,VT596 + 076H,00100000b,020h> ROMITEM <2,VT596 + 07AH,11111111b,094h> ROMITEM <2,VT596 + 07BH,11111111b,002h> ROMITEM <2,VT596 + 080H,11110000b,030h> endif; PCS1_Use_294h ifdef PCS0_Decode ifdef VT686 ;R29 - starts ROMITEM <2,VT596 + 076H,00010010b,012h> ROMITEM <2,VT596 + 077H,00000100b,004h> ; Enable PCS0 IO Trap ROMITEM <2,VT596 + 078H,11111111b,(PCS0_Decode AND 00FFh)> ROMITEM <2,VT596 + 079H,11111111b,(PCS0_Decode shr 8)> ROMITEM <2,VT596 + 080H,00001111b,PCS0_Decode_Width> else; VT686 ;R29 - ends ROMITEM <2,VT596 + 076H,00010000b,010h> ROMITEM <2,VT596 + 078H,11111111b,(PCS0_Decode AND 00FFh)> ROMITEM <2,VT596 + 079H,11111111b,(PCS0_Decode shr 8)> ROMITEM <2,VT596 + 080H,00001111b,003h> endif; VT686 ;R29 endif; PCS0_Decode ifdef PCS1_Decode ROMITEM <2,VT596 + 076H,00100000b,020h> ROMITEM <2,VT596 + 07AH,11111111b,(PCS1_Decode AND 00FFh)> ROMITEM <2,VT596 + 07BH,11111111b,(PCS1_Decode shr 8)> ROMITEM <2,VT596 + 080H,11110000b,030h> endif; PCS1_Decode Public UltraMode2_Set_Mode1_Status ;R09 ifndef UltraMode2_No_Set_Mode1 ;R09 UltraMode2_Set_Mode1_Status: ;R09 ROMITEM <2,3C00H,00000001b,01h> ;Ultra Mode2 set Mode1 ;R09 endif; UltraMode2_No_Set_Mode1 ;R09 ifdef Blink_Suspend_LED_In_GPO0 ;R26 ROMITEM <2,VT586_ACPI + 54h,00000011b,000h> ;R26 endif; Blink_Suspend_LED_In_GPO0 ;R26 EndRom_Table label near public Auto_String Auto_String label near ifndef New_Auto_Table_Method db '----------',0 endif; New_Auto_Table_Method ;-----------------------; ; 692 DRAM Timing ; ;-----------------------; ifdef Have_Fast_Page_DRAM_Table ;---------------; ; Fast_Page ; ;---------------; db '66FP,S',0 ; Auto-Slow db '99FP,S',0 ; Auto-Slow db '66FP,F',0 ; Auto-Fast db '99FP,F',0 ; Auto-Fast endif; Have_Fast_Page_DRAM_Table ;---------------; ; EDO ; ;---------------; db '66ED,S',0 ;> Auto-Slow db '99ED,S',0 ;> Auto-Slow db '66ED,F',0 ;> Auto-Fast db '99ED,F',0 ;> Auto-Fast ;---------------; ; SDRAM II ; ifdef SUPPORT_SDRAM_II ;---------------; db '66S2,S',0 ;< Auto-Slow db '99S2,S',0 ;< Auto-Slow db '66S2,F',0 ;< Auto-Fast db '99S2,F',0 ;< Auto-Fast endif; SUPPORT_SDRAM_II ;---------------; ; SDRAM ; ;---------------; db '66SD,S',0 ;= Auto-Slow db '99SD,S',0 ;= Auto-Slow db '66SD,F',0 ;= Auto-Fast db '99SD,F',0 ;= Auto-Fast ;Auto-configuration items public Auto_Table public EndAuto_Table Public New_Auto_Table New_Auto_Table label near Auto_Table label near db No_Of_Auto_Item Auto_CPU_486DX: Auto_CPU_486SX: Auto_CPU_P24T: Auto_CPU_P24D: Auto_CPU_386DX: Auto_CPU_386SX: Auto_CPU_386SL: Auto_CPU_486SLC: Auto_CPU_486DLC: Auto_CPU_IBM386SLC: Auto_CPU_486S: Auto_CPU_586: Auto_CPU_486SXS: Auto_CPU_486DXS: Auto_CPU_486DX2S: Auto_CPU_IBM486DLC3: ifndef New_Auto_Table_Method dw offset Auto_40Mhz ;for 40Mhz system endif; New_Auto_Table_Method ;-----------------------; ; 692 DRAM Timing ; ;-----------------------; ;---------------; ; Fast_Page ; _FastPage_DRAM_tbl: ;---------------; ifdef Have_Fast_Page_DRAM_Table Auto_CPU_66MHz: dw offset VT692_Auto_66Mhz_FP_7 ;for 66Mhz system Auto_CPU_100MHz: dw offset VT692_Auto_100Mhz_FP_7 ;for 100Mhz system _DIFF1 EQU ($-(offset _FastPage_DRAM_tbl)) dw offset VT692_Auto_66Mhz_FP_6 ;for 66Mhz system dw offset VT692_Auto_100Mhz_FP_6 ;for 100Mhz system _DIFF2 EQU ($-(offset _FastPage_DRAM_tbl)) ;---------------; ; EDO ; ;---------------; dw offset VT692_Auto_66Mhz_ED_7 ;for 66Mhz system dw offset VT692_Auto_100Mhz_ED_7 ;for 100Mhz system dw offset VT692_Auto_66Mhz_ED_6 ;for 66Mhz system dw offset VT692_Auto_100Mhz_ED_6 ;for 100Mhz system else; Have_Fast_Page_DRAM_Table Auto_CPU_66MHz: dw offset VT692_Auto_66Mhz_ED_7 ;for 66Mhz system Auto_CPU_100MHz: ; dw offset VT692_Auto_100Mhz_ED_7 ;for 100Mhz system _DIFF1 EQU ($-(offset _FastPage_DRAM_tbl)) ; dw offset VT692_Auto_66Mhz_ED_6 ;for 66Mhz system dw offset VT692_Auto_100Mhz_ED_6 ;for 100Mhz system _DIFF2 EQU ($-(offset _FastPage_DRAM_tbl)) ; endif; Have_Fast_Page_DRAM_Table ; ;---------------; ; SDRAM II ; ifdef SUPPORT_SDRAM_II ;---------------; dw offset VT692_Auto_66Mhz_S2_10 ;for 66Mhz system dw offset VT692_Auto_100Mhz_S2_10 ;for 100Mhz system dw offset VT692_Auto_66Mhz_S2_8 ;for 66Mhz system dw offset VT692_Auto_100Mhz_S2_8 ;for 100Mhz system endif; SUPPORT_SDRAM_II ;---------------; ; SDRAM ; ;---------------; dw offset VT692_Auto_66Mhz_SD_10 ;for 66Mhz system dw offset VT692_Auto_100Mhz_SD_10 ;for 100Mhz system dw offset VT692_Auto_66Mhz_SD_8 ;for 66Mhz system dw offset VT692_Auto_100Mhz_SD_8 ;for 100Mhz system public Auto_Dx2_Table Auto_Dx2_Table label near Auto_CPU_486DX2: Auto_CPU_IBM486SLC2: Auto_CPU_486S2: EndAuto_Table label near ALIGN 4 Auto_16Mhz label near Auto_20Mhz label near Auto_25Mhz label near Auto_33Mhz label near Auto_40Mhz label near Auto_50Mhz label near Auto_60Mhz label near Auto_66Mhz label near Auto_50DX2 label near Auto_66DX2 label near ROMITEM <2,(VT692)+64h,0FFH,0ffh> ;DRAM Timing No_Of_Auto_Item EQU ($-offset Auto_66Mhz)/ROMITEM_SIZE ;-----------------------; ; 692 DRAM Timing ; ;-----------------------; ;---------------; ; Fast Page ; ;---------------; ifdef Have_Fast_Page_DRAM_Table ALIGN 4 ; => 70ns VT692_Auto_66Mhz_FP_7 label near ROMITEM <2,(VT692)+64h,0FFH,0D6h> ALIGN 4 VT692_Auto_100Mhz_FP_7 label near ROMITEM <2,(VT692)+64h,0FFH,0EEh> ALIGN 4 ; => 60ns VT692_Auto_66Mhz_FP_6 label near ROMITEM <2,(VT692)+64h,0FFH,004h> ALIGN 4 VT692_Auto_100Mhz_FP_6 label near ROMITEM <2,(VT692)+64h,0FFH,0DEh> endif; Have_Fast_Page_DRAM_Table ;---------------; ; EDO ; ;---------------; ALIGN 4 ; => 70ns VT692_Auto_66Mhz_ED_7 label near ROMITEM <2,(VT692)+64h,0FFH,0D6h> ALIGN 4 VT692_Auto_100Mhz_ED_7 label near ROMITEM <2,(VT692)+64h,0FFH,0EEh> ALIGN 4 ; => 60ns VT692_Auto_66Mhz_ED_6 label near ROMITEM <2,(VT692)+64h,0FFH,004h> ALIGN 4 VT692_Auto_100Mhz_ED_6 label near ROMITEM <2,(VT692)+64h,0FFH,0DEh> ifdef SUPPORT_SDRAM_II ;---------------; ; SDRAM II ; ;---------------; ALIGN 4 ; => 10ns VT692_Auto_66Mhz_S2_10 label near ROMITEM <2,(VT692)+64h,0CCH,000h> ALIGN 4 VT692_Auto_100Mhz_S2_10 label near ROMITEM <2,(VT692)+64h,0CCH,0C4h> ALIGN 4 ; => 8ns VT692_Auto_66Mhz_S2_8 label near ROMITEM <2,(VT692)+64h,0CCH,000h> ALIGN 4 VT692_Auto_100Mhz_S2_8 label near ROMITEM <2,(VT692)+64h,0CCH,0C4h> endif; SUPPORT_SDRAM_II ;---------------; ; SDRAM ; ;---------------; ALIGN 4 ; => 70ns VT692_Auto_66Mhz_SD_10 label near ROMITEM <2,(VT692)+64h,0CCH,000h> ALIGN 4 VT692_Auto_100Mhz_SD_10 label near ROMITEM <2,(VT692)+64h,0CCH,0C4h> ALIGN 4 ; => 60ns VT692_Auto_66Mhz_SD_8 label near ROMITEM <2,(VT692)+64h,0CCH,000h> ALIGN 4 VT692_Auto_100Mhz_SD_8 label near ROMITEM <2,(VT692)+64h,0CCH,0C4h> Chip_Feature_Start LABEL NEAR ;------------------------------------------------------------------ CF_CMOS EQU 40H ifndef USB_Item_Not_In_Cfeat ifdef USB_SUPPORT USB_CMOS EQU CF_CMOS USB_CMOS_BIT EQU 80h endif ;USB_SUPPORT endif; USB_Item_Not_In_Cfeat ;**************************************************************** ;* * ;* Add your auto cfg menuitem here. * ;* * ;* Note: this item MUST be a 1 bit item in which: * ;* i. 0 - Auto cfg DISABLED * ;* 1 - Auto cfg ENABLED * ;* ii. CMOS location wherever * ;* * ;**************************************************************** Xaxis = 15-13 Yaxis = 3 ;[]==============================================================[] ; These ITEM will be program in (POST 08h) POST BEh ; These ITEM will be program in (POST 41h) POST BFh ;[]==============================================================[] DEFINE_ITEM Bank_01_DRAM_Timing_Item menuitem <2,\ offset Bank_01_DRAM_Timing_Str,NOCT,0ffh,CF_CMOS+04h,07h,\ offset Bank01_DRAM_Timing_Val,0,7h,Xaxis,Yaxis,0h,0h,offset Bank_01_DRAM_Timing_Item_Lang_Tbl> DEFINE_ITEM Bank_23_DRAM_Timing_Item menuitem <2,\ offset Bank_23_DRAM_Timing_Str,NOCT,0ffh,CF_CMOS+04h,38h,\ offset Bank23_DRAM_Timing_Val,0,7h,Xaxis,Yaxis,0h,0h,offset Bank_23_DRAM_Timing_Item_Lang_Tbl> DEFINE_ITEM Bank_45_DRAM_Timing_Item menuitem <2,\ offset Bank_45_DRAM_Timing_Str,NOCT,0ffh,CF_CMOS+05h,07h,\ offset Bank45_DRAM_Timing_Val,0,7h,Xaxis,Yaxis,0h,0h,offset Bank_45_DRAM_Timing_Item_Lang_Tbl> ifndef FOUR_DIMM_SUPPORT IFNDEF No_Hidden_DRAM_Timing_Item ;R05 Hidden_Bank_67_DRAM_Timing_Item EQU 1 ;R05 ENDIF; No_Hidden_DRAM_Timing_Item ;R05 endif; FOUR_DIMM_SUPPORT ;R05 ifdef Hidden_Bank_67_DRAM_Timing_Item ;R05 - starts DEFINE_ITEM Bank_67_DRAM_Timing_Item menuitem Yaxis = Yaxis - 1 else; Hidden_Bank_67_DRAM_Timing_Item ;R05 - ends DEFINE_ITEM Bank_67_DRAM_Timing_Item menuitem <2,\ offset Bank_67_DRAM_Timing_Str,NOCT,0ffh,CF_CMOS+05h,38h,\ offset Bank67_DRAM_Timing_Val,0,7h,Xaxis,Yaxis,0h,0h,offset Bank_67_DRAM_Timing_Item_Lang_Tbl> endif; Hidden_Bank_67_DRAM_Timing_Item ;R05 ifndef CAS_Latency_Auto ;R31 DEFINE_ITEM SDRAM_CL_Item menuitem <2,\ offset SDRAM_CL_Str,NOCT,01h,SDRAM_CMOS,SDRAM_CL_BIT,\ offset SDRAM_CL_Val,0,1,Xaxis,Yaxis,0h,0h,offset SDRAM_CL_Item_Lang_Tbl> else; CAS_Latency_Auto ;R31 - starts DEFINE_ITEM SDRAM_CL_Item menuitem <2,\ offset SDRAM_CL_Str,NOCT,03h,SDRAM_CMOS,(SDRAM_CL_BIT+SDRAM_CMOS_BIT),\ offset SDRAM_CL_Val,0,2,Xaxis,Yaxis,SDRAM_CMOS_BIT,SDRAM_CMOS_BIT,offset SDRAM_CL_Item_Lang_Tbl> ;R10A - ends endif; CAS_Latency_Auto ;R31 - ends ifdef Have_BankInterleave_Item ifdef SDRAM_BankInterleave_Default_Enable DEFINE_ITEM SDRAM_BK_Item menuitem <2,\ offset SDRAM_BK_Str,NOCT,03h,SDRAM_CMOS,SDRAM_BK_BIT,\ offset SDRAM_BK_Val,0,3,Xaxis,Yaxis,02h,SDRAM_BK_4_BIT,offset SDRAM_BK_Item_Lang_Tbl> else; SDRAM_BankInterleave_Default_Enable DEFINE_ITEM SDRAM_BK_Item menuitem <2,\ offset SDRAM_BK_Str,NOCT,03h,SDRAM_CMOS,SDRAM_BK_BIT,\ offset SDRAM_BK_Val,0,3,Xaxis,Yaxis,0h,00h,offset SDRAM_BK_Item_Lang_Tbl> endif; SDRAM_BankInterleave_Default_Enable endif; Have_BankInterleave_Item ifndef No_Have_DRAM_Async_Item ;R10 - starts IFNDEF DRAM_Async_CMOS DRAM_Async_CMOS EQU 40h DRAM_Async_CMOS_Bit EQU 20h ENDIF; DRAM_Async_CMOS ;R10B IFDEF DRAM_Default_Run_AGP_Clock ;R10A - starts IFNDEF DRAM_Default_Run_Host_Clock ;R10B DEFINE_ITEM DRAM_Async_Item menuitem <2,\ offset DRAM_Async_Str,NOCT,01h,DRAM_Async_CMOS,DRAM_Async_CMOS_Bit,\ offset DRAM_Async_Val,0,1,Xaxis,Yaxis,0h,DRAM_Async_CMOS_Bit,offset DRAM_Async_Item_Lang_Tbl> ;R10B ELSE; DRAM_Default_Run_AGP_Clock ;R10A - ends ELSE; DRAM_Default_Run_Host_Clock ;R10B DEFINE_ITEM DRAM_Async_Item menuitem <2,\ offset DRAM_Async_Str,NOCT,01h,DRAM_Async_CMOS,DRAM_Async_CMOS_Bit,\ offset DRAM_Async_Val,0,1,Xaxis,Yaxis,0h,0h,offset DRAM_Async_Item_Lang_Tbl> ;R10B ENDIF; DRAM_Default_Run_AGP_Clock ;R10A ENDIF; DRAM_Default_Run_Host_Clock ;R10B endif; No_Have_DRAM_Async_Item ;R10 - ends ifdef Have_Page_Mode_Item DEFINE_ITEM DRAM_Page_Mode_Item menuitem <2,\ offset DRAM_Page_Mode_Str,NOCT,10h,CF_CMOS,10h,\ offset Ena_Str,0,1,Xaxis,Yaxis,10h,10h,offset DRAM_Page_Mode_Item_Lang_Tbl> endif; Have_Page_Mode_Item DEFINE_ITEM Mem_Hole_Item menuitem DEFINE_ITEM R_Around_W_Item menuitem <2,\ offset R_Around_W_Str,VT692+50h,40h,CF_CMOS+3,08h,\ offset Dis_Str,0,1,Xaxis,Yaxis,00h,00h,offset Std_Help_Str> DEFINE_ITEM Concurrent_Item menuitem <0,\ offset Concurrent_Str,VT692+51h,01h,CF_CMOS+2,04h,\ offset Dis_Str,0,1,Xaxis,Yaxis,0,0,offset Std_Help_Str> ;R16 - starts ifndef BiosCache_CMOS ;R16A BiosCache_CMOS EQU CF_CMOS+2 ;R16A BiosCache_CMOS_Bit equ 01h ;R16A endif; BiosCache_CMOS ;R16A DEFINE_ITEM BiosCache_Item menuitem <2,\ offset BiosCache_Str,NOCT,01h,BiosCache_CMOS,BiosCache_CMOS_Bit,\ offset Dis_Str,0,1,Xaxis,Yaxis,0,0,offset Std_Help_Str> ;R16A offset BiosCache_Str,NOCT,01h,CF_CMOS+2,01h,\ ifdef SEPARATE_P6_VIDEO_ITEM DEFINE_ITEM VideoRom_Item menuitem <2,\ offset VideoRomC_Str,NOCT,01h,CF_CMOS+2,02h,\ offset Dis_Str,0,1,Xaxis,Yaxis,0,0,offset Std_Help_Str> endif; SEPARATE_P6_VIDEO_ITEM ;R16 - ends DEFINE_ITEM VideoCache_Item menuitem <0,\ offset VideoCache_Str,NOCT,01h,CF_CMOS,00000001b,\ offset Dis_Str,0,1,Xaxis,Yaxis,0,0,offset NullStr> ;R36 - starts ifdef Have_IO_Recovery_Item DEFINE_ITEM IO_Recovery_Item menuitem <2,\ offset IO_Recovery_Str,VT586+040H,08h,IO_Recovery_CMOS,IO_Recovery_CMOS_BIT,\ offset Dis_Str,0,1,Xaxis,Yaxis,08h,IO_Recovery_CMOS_BIT,offset Std_Help_Str> endif; Have_IO_Recovery_Item ;R36 - ends ifdef Have_AGP_Item DEFINE_ITEM AGP_Item menuitem <2,\ offset AGP_Str,NOCT,01h,CF_CMOS+0,040h,\ offset Dis_Str,0,1,Xaxis,Yaxis,00h,040h,offset AGP_Item_Lang_Tbl> endif; Have_AGP_Item DEFINE_ITEM Aperture_Size_Item menuitem <2,\ offset Aperture_Size_Str,NOCT,07h,CF_CMOS+02h,038h,\ offset Aperture_Size_Val,0,6,Xaxis,Yaxis,02h,10h,offset Aperture_Size_Item_Lang_Tbl> ifndef AGP_CMOS AGP_CMOS EQU CF_CMOS AGP_CMOS_BIT EQU 40h endif; AGP_CMOS DEFINE_ITEM AGP_MODE_Item menuitem <2,\ offset AGP_MODE_Str,VT692+0ach,08h,AGP_CMOS,AGP_CMOS_BIT,\ offset Dis_Str,0,1,Xaxis,Yaxis,08h,AGP_CMOS_BIT,offset AGP_MODE_Item_Lang_Tbl> ifdef Jumpless_Support JUMPLESS_FOR_CFEATURE_ASM = 1 include JUMPLESS.INC endif; Jumpless_Support ;R23 - starts ifdef VT596 ifdef APC_Power_LED_ITEM DEFINE_ITEM APC_LED_ITEM menuitem <2,\ offset APC_LED_Str,NOCT,00h,APC_LED_CMOS,APC_LED_CMOS_BIT,\ offset APC_LED_val,0,1,Xaxis,Yaxis,00h,00h,offset APC_LED_ITEM_Lang_Tbl> endif; APC_Power_LED_ITEM ;R24 - starts ifdef Have_Chassis_Intrasion_Item DEFINE_ITEM Chassis_Intrasion_ITEM menuitem <2,\ offset Chassis_Intr_Str,NOCT,00h,Chassis_Intr_CMOS,Chassis_Intr_CMOS_BIT,\ offset Chassis_Intr_val,0,1,Xaxis,Yaxis,00h,00h,offset Chassis_Intrasion_ITEM_Lang_Tbl> endif; Have_Chassis_Intrasion_Item ;R24 - ends endif; VT596 ;R23 - ends ;R06 - starts ifdef OEM1_GPO_CNTL ifdef OEM1_CNTL_INVERT DEFINE_ITEM OEM1_GPO_CNTL_Item menuitem <2,\ offset OEM1_Str,NOCT,00000001b,OEM1_GPO_CNTL_CMOS,OEM1_GPO_CNTL_CMOS_Bit,\ offset Ena_Str,0,1,Xaxis,Yaxis,0H,0h,offset Std_Help_Str> else; OEM1_CNTL_INVERT DEFINE_ITEM OEM1_GPO_CNTL_Item menuitem <2,\ offset OEM1_Str,NOCT,00000001b,OEM1_GPO_CNTL_CMOS,OEM1_GPO_CNTL_CMOS_Bit,\ offset Dis_Str,0,1,Xaxis,Yaxis,0H,0h,offset Std_Help_Str> endif; OEM1_CNTL_INVERT endif; OEM1_GPO_CNTL ifdef OEM2_GPO_CNTL ifdef OEM2_CNTL_INVERT DEFINE_ITEM OEM2_GPO_CNTL_Item menuitem <2,\ offset OEM2_Str,NOCT,00000001b,OEM2_GPO_CNTL_CMOS,OEM2_GPO_CNTL_CMOS_Bit,\ offset Ena_Str,0,1,Xaxis,Yaxis,0H,0h,offset Std_Help_Str> else; OEM2_CNTL_INVERT DEFINE_ITEM OEM2_GPO_CNTL_Item menuitem <2,\ offset OEM2_Str,NOCT,00000001b,OEM2_GPO_CNTL_CMOS,OEM2_GPO_CNTL_CMOS_Bit,\ offset Dis_Str,0,1,Xaxis,Yaxis,0H,0h,offset Std_Help_Str> endif; OEM1_CNTL_INVERT endif; OEM2_GPO_CNTL ifdef OEM3_GPO_CNTL ifdef OEM3_CNTL_INVERT DEFINE_ITEM OEM3_GPO_CNTL_Item menuitem <2,\ offset OEM3_Str,NOCT,00000001b,OEM3_GPO_CNTL_CMOS,OEM3_GPO_CNTL_CMOS_Bit,\ offset Ena_Str,0,1,Xaxis,Yaxis,0H,0h,offset Std_Help_Str> else; OEM3_CNTL_INVERT DEFINE_ITEM OEM3_GPO_CNTL_Item menuitem <2,\ offset OEM3_Str,NOCT,00000001b,OEM3_GPO_CNTL_CMOS,OEM3_GPO_CNTL_CMOS_Bit,\ offset Dis_Str,0,1,Xaxis,Yaxis,0H,0h,offset Std_Help_Str> endif; OEM3_CNTL_INVERT endif; OEM3_GPO_CNTL ;R06 - ends ;R15 - starts ifdef Power_Type_Selectable DEFINE_ITEM Power_Type_Item menuitem <2,\ offset Power_Type_Str,NOCT,0000001b,Power_Type_CMOS,Power_Type_CMOS_Bit,\ offset Power_Type_Val,0,1,Xaxis,Yaxis,Power_Type_CMOS_Bit,Power_Type_CMOS_Bit,offset Std_Help_Str> endif; Power_Type_Selectable ;R15 - ends ;R07B ifndef USB_Item_In_Left ;R07 ;R07B IFNDEF CLKGEN_Item_In_Left ;R07A ;R07B Yaxis = 23 ;R07B ENDIF; CLKGEN_Item_In_Left ;R07A ;R07B endif; USB_Item_In_Left ;R07 ifndef USB_Item_Not_In_Cfeat ifdef VT586_USB IFDEF VT586_USB_2 ;R17 - starts ifdef USB2_Separate_Control ;R22 - starts DEFINE_ITEM ONBD_USB_Item menuitem <0,\ offset ONBD_USB_Str,NOCT,01h,CF_CMOS+2,040h,\ offset Ena_Str,0,1,Xaxis,Yaxis,00h,000h,offset Std_Help_Str> DEFINE_ITEM ONBD_USB_2_Item menuitem <0,\ offset ONBD_USB_2_Str,NOCT,01h,CF_CMOS+2,002h,\ offset Ena_Str,0,1,Xaxis,Yaxis,00h,000h,offset Std_Help_Str> else; USB2_Separate_Control ;R22 - ends DEFINE_ITEM ONBD_USB_Item menuitem <0,\ offset ONBD_USB_Str,NOCT,04h,CF_CMOS+2,040h,\ offset Ena_Str,0,1,Xaxis,Yaxis,00h,000h,offset ONBD_USB_Item_Lang_Tbl> endif; USB2_Separate_Control ;R22 ELSE; VT586_USB_2 ;R17 - ends DEFINE_ITEM ONBD_USB_Item menuitem <0,\ offset ONBD_USB_Str,NOCT,04h,CF_CMOS+2,040h,\ offset Ena_Str,0,1,Xaxis,Yaxis,04h,040h,offset ONBD_USB_Item_Lang_Tbl> ENDIF;VT586_USB_2 ;R17 ifdef USB_SUPPORT DEFINE_ITEM Usb_Legacy_Item menuitem <0,\ offset UsbLegacy_Str,NOCT,USB_CMOS_BIT,USB_CMOS,USB_CMOS_BIT,\ offset Dis_Str,0,1,Xaxis,Yaxis,0,0,offset Usb_Legacy_Item_Lang_Tbl> IFDEF USB_MOUSE_SUPPORT ;R34 - starts DEFINE_ITEM USB_Mouse_Item menuitem <0,\ offset UsbLegacy_Mouse_Str,NOCT,USB_MOUSE_CMOS_BIT,USB_MOUSE_CMOS,USB_MOUSE_CMOS_BIT,\ offset Dis_Str,0,1,Xaxis,Yaxis,0,0,offset Usb_Legacy_Item_Lang_Tbl> ENDIF;USB_MOUSE_SUPPORT ;R34 - ends endif ;USB_SUPPORT endif ;VT586_USB endif; USB_Item_Not_In_Cfeat ifndef TV_OUT_ITEM_IN_IOFEAT ;R25A ;R25 - starts ifdef Issue_Gemlight_TV_Out_Function DEFINE_ITEM TV_Out_Mode_Item menuitem <0,\ offset TV_Out_Mode_Str,NOCT,TV_Out_Mode_CMOS_BIT,TV_Out_Mode_CMOS,TV_Out_Mode_CMOS_BIT,\ offset TV_Out_Mode_Val,0,1,Xaxis,Yaxis,0,0,offset TV_Out_Mode_Item_Lang_Tbl> endif; Issue_Gemlight_TV_Out_Function ;R25 - ends endif; TV_OUT_ITEM_IN_IOFEAT ;R25A ;R20 - starts ifdef VT686 DEFINE_ITEM ONBD_AC97_Item menuitem <0,\ offset ONBD_AC97_Str,VT586+85h,04h,CF_CMOS+2,080h,\ offset Ena_Str,0,1,Xaxis,Yaxis,00h,000h,offset Std_Help_Str> DEFINE_ITEM ONBD_MC97_Item menuitem <0,\ offset ONBD_MC97_Str,VT586+85h,08h,CF_CMOS+3,080h,\ offset Ena_Str,0,1,Xaxis,Yaxis,00h,000h,offset Std_Help_Str> endif; VT686 ;R20 - ends ;R28 - starts ifdef MOV_WO_ITEM_TO_CFEATURE ifndef WO_CMOS WO_CMOS EQU 55h endif; WO_CMOS IFNDEF VT596 ifdef Wake_On_EXTSMI0_Support DEFINE_ITEM WO_Item menuitem endif; Wake_On_EXTSMI0_Support ELSE; VT596 ifdef Wake_On_GPI_Support DEFINE_ITEM WO_Item menuitem endif; Wake_On_GPI_Support ifdef WAKE_LAN_BY_LID DEFINE_ITEM WO_Item menuitem endif; WAKE_LAN_BY_LID ;R33 ifdef LAN_Ctrl_BY_LID ;R33 DEFINE_ITEM WO1_Item ;R33 menuitem ;R33 endif; LAN_Ctrl_BY_LID ENDIF; VT596 endif; MOV_WO_ITEM_TO_CFEATURE ;R28 - ends ;---------------; ; JMP to RIGHT ; ;---------------; ;R07B ifdef USB_Item_In_Left ;R07 IFNDEF CFEATURE_NO_SPLIT ;R07B IFNDEF CLKGEN_Item_In_Left ;R07A Yaxis = 23 ;R07 ENDIF; CLKGEN_Item_In_Left ;R07A ENDIF; CFEATURE_NO_SPLIT ;R07B ;R07B endif; USB_Item_In_Left ;R07 ;R07B ifndef Dont_Add_Blank_Line_Before_Sensor ;R07B Yaxis = Yaxis + 1 ;R07B endif; Dont_Add_Blank_Line_Before_Sensor IF CLKCNTL_IN_CFEATURE include CLKCNTL.MNU ENDIF; CLKCNTL_IN_CFEATURE IFNDEF CFEATURE_NO_SPLIT ;R07B ifdef CLKGEN_Item_In_Left ;R07A Yaxis = 23 ;R07A endif; CLKGEN_Item_In_Left ;R07A ENDIF; CFEATURE_NO_SPLIT ;R07B if SENSOR_IN_CFEATURE include sensor.mnu endif; SENSOR_IN_CFEATURE Chip_Feature_End LABEL NEAR ;---------------------------------------------------------- CHIP_ITEM_NO EQU $-offset CHIP_Feature_START IF CHIP_ITEM_NO EQ 0 CHIP_STAT EQU ITEMDISABLE+0 ELSE CHIP_STAT EQU 0 ENDIF ;---------------------------------------------------------- ;R12 Bank01_Dram_Timing_Val db 'EDO 60ns ',0 ;R12 db 'EDO 50ns ',0 ;R12 db 'Normal ',0 ;R12 db 'Medium ',0 ;R12 db 'Fast ',0 ;R12 db 'Turbo ',0 ;R12 Bank01_Dram_Timing_Val_ db 'SDRAM 10ns',1 ;R12 db 'SDRAM 8ns',1 ;R12 ;R12 Bank23_Dram_Timing_Val db 'EDO 60ns ',0 ;R12 db 'EDO 50ns ',0 ;R12 db 'Normal ',0 ;R12 db 'Medium ',0 ;R12 db 'Fast ',0 ;R12 db 'Turbo ',0 ;R12 Bank23_Dram_Timing_Val_ db 'SDRAM 10ns',1 ;R12 db 'SDRAM 8ns',1 ;R12 ;R12 Bank45_Dram_Timing_Val db 'EDO 60ns ',0 ;R12 db 'EDO 50ns ',0 ;R12 db 'Normal ',0 ;R12 db 'Medium ',0 ;R12 db 'Fast ',0 ;R12 db 'Turbo ',0 ;R12 Bank45_Dram_Timing_Val_ db 'SDRAM 10ns',1 ;R12 db 'SDRAM 8ns',1 ;R12 ;R12 Bank67_Dram_Timing_Val db 'EDO 60ns ',0 ;R12 db 'EDO 50ns ',0 ;R12 db 'Normal ',0 ;R12 db 'Medium ',0 ;R12 db 'Fast ',0 ;R12 db 'Turbo ',0 ;R12 Bank67_Dram_Timing_Val_ db 'SDRAM 10ns',1 ;R12 db 'SDRAM 8ns',1 ;R12 - starts Bank01_Dram_Timing_Val db 'SDRAM 10ns',0 db 'SDRAM 8ns',0 db 'Normal ',0 db 'Medium ',0 db 'Fast ',0 db 'Turbo ',0 Bank01_Dram_Timing_Val_ db 'EDO 60ns ',1 db 'EDO 50ns ',1 Bank23_Dram_Timing_Val db 'SDRAM 10ns',0 db 'SDRAM 8ns',0 db 'Normal ',0 db 'Medium ',0 db 'Fast ',0 db 'Turbo ',0 Bank23_Dram_Timing_Val_ db 'EDO 60ns ',1 db 'EDO 50ns ',1 Bank45_Dram_Timing_Val db 'SDRAM 10ns',0 db 'SDRAM 8ns',0 db 'Normal ',0 db 'Medium ',0 db 'Fast ',0 db 'Turbo ',0 Bank45_Dram_Timing_Val_ db 'EDO 60ns ',1 db 'EDO 50ns ',1 Bank67_Dram_Timing_Val db 'SDRAM 10ns',0 db 'SDRAM 8ns',0 db 'Normal ',0 db 'Medium ',0 db 'Fast ',0 db 'Turbo ',0 Bank67_Dram_Timing_Val_ db 'EDO 60ns ',1 db 'EDO 50ns ',1 ;R12 - ends Bank_01_DRAM_Timing_Str DB 'Bank 0/1 DRAM Timing : ',0 Bank_23_DRAM_Timing_Str DB 'Bank 2/3 DRAM Timing : ',0 Bank_45_DRAM_Timing_Str DB 'Bank 4/5 DRAM Timing : ',0 Bank_67_DRAM_Timing_Str DB 'Bank 6/7 DRAM Timing : ',0 SDRAM_CL_Str db 'SDRAM Cycle Length : ',0 ifdef CAS_Latency_Auto ;R31 SDRAM_CL_Val db '3 ',0 ;R31 db '2 ',0 ;R31 db 'Auto',0 ;R31 else; CAS_Latency_Auto ;R31 SDRAM_CL_Val db '3', 0 db '2', 0 endif; CAS_Latency_Auto ;R31 ifdef Have_BankInterleave_Item SDRAM_BK_Str db 'SDRAM Bank Interleave: ',0 SDRAM_BK_Val db 'Disabled',0 db '2 Bank ',0 db '4 Bank ',0 endif; Have_BankInterleave_Item ifndef No_Have_DRAM_Async_Item ;R10 - starts DRAM_Async_Str db 'DRAM Clock : ',0 DRAM_Async_Val db 'Host CLK',0 ;R32 db '66 MHz ',0 Public DRAM_Async_Val_ ;R32 DRAM_Async_Val_ db '66 MHz ',0 ;R32 endif; No_Have_DRAM_Async_Item ;R10 - ends ifdef Have_Page_Mode_Item DRAM_Page_Mode_Str db 'DRAM Page-Mode : ',0 endif; Have_Page_Mode_Item Hole_Str db 'Memory Hole : ',0 Hole_Val db 'Disabled ', 0 db '512K-640K', 1 db '15M - 16M', 0 db '14M - 16M', 1 R_Around_W_Str db 'Read Around write : ',0 Concurrent_Str db 'Concurrent PCI/Host : ',0 ;R16 - starts BiosCache_Str db 'System BIOS Cacheable : ',0 ifdef SEPARATE_P6_VIDEO_ITEM VideoRomC_Str db 'Video BIOS Cacheable : ',0 endif; SEPARATE_P6_VIDEO_ITEM ;R16 - ends VideoCache_Str db 'Video RAM Cacheable : ',0 ;R36 - starts ifdef Have_IO_Recovery_Item IO_Recovery_Str DB 'I/O Recovery Time : ',0 endif; Have_IO_Recovery_Item ;R36 - ends ifdef Have_AGP_Item AGP_Str DB 'AGP : ',0 endif; Have_AGP_Item Aperture_Size_Str DB 'AGP Aperture Size : ',0 Aperture_Size_Val DB '256M',1 ;R11 ;R11 Aperture_Size_Val DB '256M',0 DB '128M',0 DB '64M ',0 DB '32M ',0 DB '16M ',0 DB '8M ',0 DB '4M ',0 AGP_MODE_Str db 'AGP-2X Mode : ',0 ifdef Jumpless_Support JUMPLESS_FOR_CFEATURE_ASM = 2 include JUMPLESS.INC endif; Jumpless_Support ;R06 - starts ifdef OEM1_GPO_CNTL OEM1_Str db OEM1_GPO_CNTL_Str endif; OEM1_GPO_CNTL ifdef OEM2_GPO_CNTL OEM2_Str db OEM2_GPO_CNTL_Str endif; OEM2_GPO_CNTL ifdef OEM3_GPO_CNTL OEM3_Str db OEM3_GPO_CNTL_Str endif; OEM3_GPO_CNTL ;R06 - ends ;R23 - starts ifdef VT596 ifdef APC_Power_LED_ITEM APC_LED_Str db 'APC Power LED : ',0 APC_LED_val db 'Disable',0 db 'Enable ',0 endif; APC_Power_LED_ITEM ;R24 - starts ifdef Have_Chassis_Intrasion_Item Chassis_Intr_Str db 'Chassis Intrasion : ',0 Chassis_Intr_val db 'Disable',0 db 'Enable ',0 endif; Have_Chassis_Intrasion_Item ;R24 - ends endif; VT596 ;R23 - ends ;R15 - starts ifdef Power_Type_Selectable Power_Type_Str db 'Power-Supply Type : ',0 Power_Type_Val db 'AT ',0 db 'ATX ',0 endif; Power_Type_Selectable ;R15 - ends ifndef TV_OUT_ITEM_IN_IOFEAT ;R25A ;R25 - starts ifdef Issue_Gemlight_TV_Out_Function TV_Out_Mode_Str db 'TV OUT Mode : ', 0 TV_Out_Mode_Val db 'NSTL ',0 db 'APL ',0 endif;Issue_Gemlight_TV_Out_Function ;R25 - ends endif; TV_OUT_ITEM_IN_IOFEAT ;R25A ifndef USB_Item_Not_In_Cfeat ifdef VT586_USB ;R07B IFNDEF USB_Item_In_Left ;R07 ;R07BONBD_USB_Str db 'OnChip USB : ',0 ;R07B ELSE; USB_Item_In_Left ;R07 - starts ifdef USB2_Separate_Control ;R22 - starts ONBD_USB_Str db 'OnChip USB : ', 0 ONBD_USB_2_Str db 'OnChip USB 2 : ', 0 else; USB2_Separate_Control ;R22 - ends ONBD_USB_Str db 'OnChip USB : ',0 endif; USB2_Separate_Control ;R22 ;R07B ENDIF; USB_Item_In_Left ;R07 - ends ifdef USB_SUPPORT ;R07B IFNDEF USB_Item_In_Left ;R07 ;R07BUsbLegacy_Str db 'USB Keyboard Support : ',0 ;R07B ELSE; USB_Item_In_Left ;R07 - starts UsbLegacy_Str db 'USB Keyboard Support : ',0 ;R07B ENDIF; USB_Item_In_Left ;R07 - ends IFDEF USB_MOUSE_SUPPORT ;R34 - starts UsbLegacy_Mouse_Str db 'USB Mouse Support : ',0 ENDIF;USB_MOUSE_SUPPORT ;R34 - ends endif ;USB_SUPPORT endif ;VT586_USB endif; USB_Item_Not_In_Cfeat ifdef VT686 ;R20 ONBD_AC97_Str db 'OnChip Sound : ', 0 ;R20 ONBD_MC97_Str db 'OnChip Modem : ', 0 ;R20 endif; VT686 ;R20 ;R28 - starts ifdef MOV_WO_ITEM_TO_CFEATURE IFNDEF VT596 ifdef Wake_On_EXTSMI0_Support IFDEF WOL_String_In_Wake_On_EXTSMI0_Support WO_Str db 'Wake Up On LAN : ',0 ELSE; WOL_String_In_Wake_On_EXTSMI0_Support WO_Str db 'EXTSMI0 Resume : ',0 ENDIF; WOL_String_In_Wake_On_EXTSMI0_Support endif; Wake_On_EXTSMI0_Support ELSE; VT596 ifdef Wake_On_GPI_Support IFDEF WOL_String_In_Wake_On_GPI_Support WOL_Str db 'Wake Up On LAN : ',0 ELSE; WOL_String_In_Wake_On_GPI_Support WOL_Str db 'GPI Resume : ',0 ENDIF; WOL_String_In_Wake_On_GPI_Support endif; Wake_On_GPI_Support ifdef WAKE_LAN_BY_LID WOL_Str db 'Wake Up On LAN : ',0 endif; WAKE_LAN_BY_LID ;R33 ifdef LAN_Ctrl_BY_LID ;R33 WOL1_Str db 'Wake Up On LAN : ',0 ;R33 endif; LAN_Ctrl_BY_LID ENDIF; VT596 endif; MOV_WO_ITEM_TO_CFEATURE ;R28 - ends ;--------------------------------------------------------------------- COLLON_LOC = 25 if SENSOR_IN_CFEATURE include sensor.str endif; SENSOR_IN_CFEATURE IF CLKCNTL_IN_CFEATURE include CLKCNTL.STR ENDIF; CLKCNTL_IN_CFEATURE ;[]======================================================================[] ;Function : Decide whether a item's BIOS default is to be programmed ; (in PRG_CHIPSET_DEFAULT) or not! ; ; Usage: ; if you have a item AT_CLOCK, for example, such that ; its meaning is varies upon different CPU. The ordinary ; way of doing this item is setup is to define: ; ; ; Clock_486_Item: ; menuitem <0,\ ; offset AT_Clock_486_Str,\ ; 25h,00000011b,34H,00000011b,\ ; offset Clk_Div_6_Str,0,4,\ ; Xaxis,Yaxis,0,0,offset Std_Help_Str> ; Clock_386_Item: ; menuitem <0,\ ; offset AT_Clock_386_Str,\ ; 25h,00000011b,34H,00000011b,\ ; offset Clk_Div_6_Str_1,0,4,\ ; Xaxis,Yaxis,0,0,offset Std_Help_Str> ; ; and then to disable/enable the correct item during run time. ; ; Howerver, the BIOS default value of the Clock_386_Item will ; be overwritten to register 25h whatever the BIOS default of ; Clock_386_Item is!. ; ; So define SPECIALPRG for both items. Then in this routine ; ; Clock_386_Item: ; Return CF if CPU type != 386 ; Return NC if CPU type = 386 ; Clock_486_Item: ; Return CF if CPU type != 486 ; Return NC if CPU type = 486 ; ; Example: see 214UC000.ASM (CFEATURE) ; ;Input : BX point to menuitem ; ;Output : CF - this item should not be programmed ; NC - this item should be programmed ; ;Registers : BX, SI, DI must be preserved ; ;Note : 1. no stack available ; 2. call from PRG_CHIPSET_DEFAULT in ct_table.asm ;[]======================================================================[] Public Cf_Special_Prg Cf_Special_Prg Proc Near clc ret Cf_Special_Prg Endp ;[]==============================================================[] ;Ct_ReTable_Auto: ; Modify auto-table offset to program registers and to load setup ; defaults for auto-configuration if system support 1x & 2x clocks ; and it can detected by software. ;Save : all but SI ;Input : si : normal offset of auto-table ( referenced by CPU type ) ;Output: si : modified offset of auto_table ;Note : 1. Read clock phase from register or I/O port. ; 2. Modify SI to second table if 2x clock installed ; 3. You must build two sets of auto-table for 1x & 2x ; clock ; 4. See 214k5000.asm for instance ;[]==============================================================[] public Ct_ReTable_Auto Ct_ReTable_Auto proc near xcall X_Ct_Retable_Auto ret Ct_ReTable_Auto endp ;--------------------------------------------------------------------- ifndef USB_Item_Not_In_Cfeat ifdef VT586_USB ifdef USB_SUPPORT ifndef USB2_Separate_Control ;R22 - starts Show_USB_Legacy proc near mov cx, 01 mov di, offset USB_Legacy_Tbl call If_CX_Then_Dis ret USB_Legacy_Tbl: dw offset USB_Legacy_Item IFDEF USB_MOUSE_SUPPORT ;R34 dw offset USB_Mouse_Item ;R34 ENDIF;USB_MOUSE_SUPPORT ;R34 dw -1 Show_USB_Legacy endp endif; USB2_Separate_Control ;R22 - ends endif ;USB_SUPPORT endif ;VT586_USB endif; USB_Item_Not_In_Cfeat ifdef Jumpless_Support JUMPLESS_FOR_CFEATURE_ASM = 4 include JUMPLESS.INC endif; Jumpless_Support FCODE ENDS ;-------------------------------------------------------------- ;-------------------------------------------------------------- ;----- The following codes will be located at E000 ! ---------- ;----- The following codes will be located at E000 ! ---------- ;----- The following codes will be located at E000 ! ---------- ;----- The following codes will be located at E000 ! ---------- ;-------------------------------------------------------------- ;-------------------------------------------------------------- .386 ECODE SEGMENT USE16 PARA PUBLIC 'ECODE' ASSUME CS:EGROUP, ES:EGROUP if SENSOR_IN_CFEATURE ifndef SENSOR_IN_XGROUP ;R27 include sensor.e8 endif ;SENSOR_IN_XGROUP ;R27 endif; SENSOR_IN_CFEATURE ECODE ENDS IF CLKCNTL_IN_CFEATURE include clkcntl.xgp ENDIF; CLKCNTL_IN_CFEATURE .386 XGROUP GROUP XCODE XCODE SEGMENT USE16 PARA PUBLIC 'XCODE' ASSUME CS:XGROUP,ES:XGROUP ;R19 DEFINE_ITEM_MSG Bank_01_DRAM_Timing_Item,Bank_01_DRAM_Timing_Str,DRAM_Timing_Val, ,NEED_STD_HELP ;R19 DEFINE_ITEM_MSG Bank_23_DRAM_Timing_Item,Bank_23_DRAM_Timing_Str,DRAM_Timing_Val, ,NEED_STD_HELP ;R19 DEFINE_ITEM_MSG Bank_45_DRAM_Timing_Item,Bank_45_DRAM_Timing_Str,DRAM_Timing_Val, ,NEED_STD_HELP ;R19 DEFINE_ITEM_MSG Bank_67_DRAM_Timing_Item,Bank_67_DRAM_Timing_Str,DRAM_Timing_Val, ,NEED_STD_HELP DEFINE_ITEM_MSG Bank_01_DRAM_Timing_Item,,,,NEED_STD_HELP ;R19 DEFINE_ITEM_MSG Bank_23_DRAM_Timing_Item,,,,NEED_STD_HELP ;R19 DEFINE_ITEM_MSG Bank_45_DRAM_Timing_Item,,,,NEED_STD_HELP ;R19 DEFINE_ITEM_MSG Bank_67_DRAM_Timing_Item,,,,NEED_STD_HELP ;R19 DEFINE_ITEM_MSG SDRAM_CL_Item, SDRAM_CL_Str, SDRAM_CL_Val, ,NEED_STD_HELP ifdef Have_BankInterleave_Item DEFINE_ITEM_MSG SDRAM_BK_Item, SDRAM_BK_Str, Dis_Str, ,NEED_STD_HELP endif; Have_BankInterleave_Item ifndef No_Have_DRAM_Async_Item ;R10 - starts ;R19 DEFINE_ITEM_MSG DRAM_Async_Item, DRAM_Async_Str, Dis_Str, ,NEED_STD_HELP DEFINE_ITEM_MSG DRAM_Async_Item, , , ,NEED_STD_HELP ;R19 endif; No_Have_DRAM_Async_Item ;R10 - ends ifdef Have_Page_Mode_Item DEFINE_ITEM_MSG DRAM_Page_Mode_Item, DRAM_Page_Mode_Str, Dis_Str, ,NEED_STD_HELP endif; Have_Page_Mode_Item ;R19 DEFINE_ITEM_MSG Read_PipeLine_Item, Read_PipeLine_Str, Dis_Str, ,NEED_STD_HELP DEFINE_ITEM_MSG Read_PipeLine_Item, , , ,NEED_STD_HELP ;R19 ifdef Have_Tag_RAM_Item DEFINE_ITEM_MSG Tag_RAM_Item, Tag_RAM_Str, Tag_RAM_Val, ,NEED_STD_HELP endif; Have_Tag_RAM_Item ;R19 ifdef Special_Tag_Item_Str ;R19 DEFINE_ITEM_MSG Tag_Item, Tag_Str, Tag_Val, ,NEED_STD_HELP ;R19 else; Special_Tag_Item_Str ;R19 DEFINE_ITEM_MSG Tag_Item, Tag_Str, Ena_Str, ,NEED_STD_HELP ;R19 endif; Special_Tag_Item_Str ;R19 DEFINE_ITEM_MSG PipeLine_Item, PipeLine_Str, Dis_Str, ,NEED_STD_HELP DEFINE_ITEM_MSG Tag_Item, , , ,NEED_STD_HELP ;R19 DEFINE_ITEM_MSG PipeLine_Item, , , ,NEED_STD_HELP ;R19 DEFINE_ITEM_MSG R_Around_W_Item, R_Around_W_Str, Dis_Str, ,NEED_STD_HELP DEFINE_ITEM_MSG Cache_Timing_Item, , , ,NEED_STD_HELP ifdef Have_Linear_Burst_Item DEFINE_ITEM_MSG Linear_Burst_Item, Linear_Burst_Str, Dis_Str, ,NEED_STD_HELP endif ;Have_Linear_Burst_Item DEFINE_ITEM_MSG C000_Cache_Item, , , ,NEED_STD_HELP DEFINE_ITEM_MSG F000_Cache_Item, , , ,NEED_STD_HELP DEFINE_ITEM_MSG Mem_Hole_Item, Hole_Str, Hole_Val, ,NEED_STD_HELP ifdef Have_AGP_Item DEFINE_ITEM_MSG AGP_Item, AGP_Str, Dis_Str, ,NEED_STD_HELP endif; Have_AGP_Item DEFINE_ITEM_MSG Aperture_Size_Item, Aperture_Size_Str, Aperture_Size_Val, ,NEED_STD_HELP DEFINE_ITEM_MSG AGP_MODE_Item, AGP_MODE_Str, AGP_MODE_Val, ,NEED_STD_HELP ;R23 - starts ifdef VT596 ifdef APC_Power_LED_ITEM DEFINE_ITEM_MSG APC_LED_Item, APC_LED_Str, APC_LED_Val, ,NEED_STD_HELP endif; APC_Power_LED_ITEM ;R24 - starts ifdef Have_Chassis_Intrasion_Item DEFINE_ITEM_MSG Chassis_Intrasion_Item,Chassis_Intr_Str, Chassis_Intr_Val, ,NEED_STD_HELP endif; Have_Chassis_Intrasion_Item ;R24 - end endif; VT596 ;R23 - ends ifdef Have_M2_Extra_SADS_Item DEFINE_ITEM_MSG M2_Extra_SADS_Item, M2_Extra_SADS_Str, Dis_Str, ,NEED_STD_HELP endif; Have_M2_Extra_SADS_Item ifdef Auto_Control_CPU_Voltage ifdef Free_Auto_Control_CPU_Voltage ifdef Gemlight_Auto_Control_CPU_Voltage ifdef WIN_Auto_Control_CPU_Voltage ifdef GLOBE_Auto_Control_CPU_Voltage ifdef SD_Auto_Control_CPU_Voltage DEFINE_ITEM_MSG CPU_v_Item, CPU_v_Str, CPU_v_Val, ,NEED_STD_HELP endif; SD_Auto_Control_CPU_Voltage endif; GLOBE_Auto_Control_CPU_Voltage endif; WIN_Auto_Control_CPU_Voltage endif; Gemlight_Auto_Control_CPU_Voltage endif; Free_Auto_Control_CPU_Voltage endif; Auto_Control_CPU_Voltage ifdef Auto_CPU_Ratio DEFINE_ITEM_MSG CPU_Ratio_Item, CPU_Ratio_Str, CPU_Ratio_Val, ,NEED_STD_HELP endif; Auto_CPU_Ratio ifdef Auto_Control_CPU_Voltage DEFINE_ITEM_MSG CPU_v_Item, CPU_v_Str, CPU_v_Val, ,NEED_STD_HELP endif ;Auto_Control_CPU_Voltage ifndef TV_OUT_ITEM_IN_IOFEAT ;R25A ;R25 - starts ifdef Issue_Gemlight_TV_Out_Function DEFINE_ITEM_MSG TV_Out_Mode_Item, TV_Out_Mode_Str, TV_Out_Mode_Val, ,NEED_STD_HELP endif;Issue_Gemlight_TV_Out_Function ;R25 - ends endif; TV_OUT_ITEM_IN_IOFEAT ;R25A ifndef USB_Item_Not_In_Cfeat ifdef VT586_USB DEFINE_ITEM_MSG ONBD_USB_Item, ONBD_USB_Str, Ena_Str, ,NEED_STD_HELP ifdef USB_SUPPORT DEFINE_ITEM_MSG Usb_Legacy_Item, UsbLegacy_Str, Dis_Str, ,NEED_STD_HELP endif ;USB_SUPPORT endif ;VT586_USB endif; USB_Item_Not_In_Cfeat ;R28 - starts ifdef MOV_WO_ITEM_TO_CFEATURE IFNDEF VT596 ifdef Wake_On_EXTSMI0_Support DEFINE_ITEM_MSG WO_Item, WO_Str, Dis_Str, ,NEED_STD_HELP endif; Wake_On_EXTSMI0_Support ELSE; VT596 ifdef Wake_On_GPI_Support DEFINE_ITEM_MSG WO_Item, WO_Str, Dis_Str, ,NEED_STD_HELP endif; Wake_On_GPI_Support ifdef WAKE_LAN_BY_LID ;R08 DEFINE_ITEM_MSG WO_Item, WOL_Str, Dis_Str, ,NEED_STD_HELP DEFINE_ITEM_MSG WO_Item, , Dis_Str, ,NEED_STD_HELP endif; WAKE_LAN_BY_LID ;R33 ifdef LAN_Ctrl_BY_LID ;R33 DEFINE_ITEM_MSG WO1_Item, , Dis_Str, ,NEED_STD_HELP ;R33 endif; LAN_Ctrl_BY_LID ENDIF; VT596 endif; MOV_WO_ITEM_TO_CFEATURE ;R28 - ends ifdef Have_BankInterleave_Item IFDEF Have_Page_Mode_Item ;[]==============================================================[] ; ; Procedure : Test_DRAM ; ; Test the slowest of DRAM type for porgraming DRAM Timing ; ; Input : None ; ; Use Register : AX,BX,CX,DX ; ; Use Procedure : X_Get_Ct ; ; Note : Don't destory SI ( Auto_CFG_Table Used ) ; BX ( Setup Used ) ; ; Output : AL = 00000001b, FP ; AL = 00000011b, EDO ; AL = 00000111b, BEDO ; AL = 00001111b, SDRAM ; ;[]==============================================================[] Public Test_DRAM Test_DRAM Proc Near push gs pushad ; Save all register value ;-------------------------------; ; Test Every Bank DRAM exist ? ; ;-------------------------------; xor bx,bx ; bit of bl means bank exist ? mov cx, VT692 + 5bh Check_Bank_Exist: shl bl,1 call X_Get_Ct cmp al,bh mov bh, al jz short Next_Bank or bl, 1 ; Bank is exist Next_Bank: add cx,2 cmp cx,VT692 + 59h je short Check_Bank_Exist_End cmp cx,VT692 + 61h jne Not_Bank_67 mov cx,VT692 + 57h Not_Bank_67: jmp short Check_Bank_Exist Check_Bank_Exist_End: ; bit of bl means bank exist ? ; bit 3 : bank 0/1 (1:exist) ; bit 2 : bank 2/3 (0:none ) ; bit 1 : bank 4/5 ; bit 0 : bank 6/7 ;-------------------------------; ; Detect Every Bank DRAM type ? ; ;-------------------------------; ;***************; ; Bank 0/1 ; ;***************; mov cx, VT692 + 60h ; Get DRAM Type bit0-5 = call X_Get_Ct ; Bank0-5 DRAM Type push ax pop cx ; CX = AX = Reg 60h Value push ax ; save Reg 60h Value mov al,0f1h ; AL = 11110001b and cl,0011b ; Get Bank0/1 DRAM Type bit1,0 rol al,cl mov dl,al test bl,08h ; bit2 = bank 0/1 if exist jnz short @f ; Yes, jmp mov dl,0fh ; No, dl=Bank0/1 DRAM is None @@: ; dl = Bank0/1 DRAM Type ; Bit3-0 ; 0001 : Fast Page ; 0011 : EDO ; 0111 : Burst EDO ; 1111 : SDRAM or No DRAM ;***************; ; Bank 4/5 ; ;***************; pop ax ; Get DRAM Type bit3,2 = push ax shr ax,4 ; Bank4/5 DRAM Type mov cl,al ; CL bit1,0 = Bank4/5 DRAM Type and cl,0011b ; Get Bank4/5 DRAM Type bit1,0 mov al,0f1h ; AL = 11110001b rol al,cl mov bh,al test bl,02h ; bit0 = bank 4/5 if exist jnz short @f ; Yes, jmp mov bh,0fh ; bh = Bank4/5 DRAM is None @@: ; bh = Bank4/5 DRAM Type ; Bit3-0 ; 0001 : Fast Page ; 0011 : EDO ; 0111 : Burst EDO ; 1111 : SDRAM or No DRAM ;***************; ; Bank 2/3 ; ;***************; pop ax ; Get DRAM Type bit3,2 = push ax shr ax,2 ; Bank2/3 DRAM Type mov cl,al ; CL bit1,0 = Bank2/3 DRAM Type mov al,0f1h ; AL = 11110001b and cl,0011b ; Get Bank2/3 DRAM Type bit1,0 rol al,cl mov dh,al test bl,04h ; bit1 = bank 2/3 if exist jnz short @f ; Yes, jmp mov dh,0fh ; dh = Bank2/3 DRAM is None @@: ; dh = Bank2/3 DRAM Type ; Bit3-0 ; 0001 : Fast Page ; 0011 : EDO ; 0111 : Burst EDO ; 1111 : SDRAM or No DRAM ;***************; ; Bank 6/7 ; ;***************; pop ax ; Get DRAM Type bit7,6 = shr ax,6 ; Bank6/7 DRAM Type mov cl,al ; CL bit1,0 = Bank6/7 DRAM Type and cl,0011b ; Get Bank6/7 DRAM Type bit1,0 mov al,0f1h ; AL = 11110001b rol al,cl test bl,01h ; bit0 = bank 6/7 if exist jnz short @f ; Yes, jmp mov al,0fh ; bh = Bank6/7 DRAM is None @@: mov bl,al ; bl = Bank6/7 DRAM Type ; Bit3-0 ; 0001 : Fast Page ; 0011 : EDO ; 0111 : Burst EDO ; 1111 : SDRAM or No DRAM ;---------------------------------------; ; Detect the slowest of DRAM Type? ; ;---------------------------------------; and dl,0fh ; AL : bit 3-0 and dl,dh ; Detect the slowest of and dl,bh ; DRAM Type and dl,bl ; mov al,dl ; 0001 : Fast Page ; 0011 : EDO ; 0111 : Burst EDO ; 1111 : SDRAM Detect_End: mov gs,ax popad ; Restore all Register Value mov ax,gs pop gs ret Test_DRAM endp ENDIF;Have_Page_Mode_Item endif; Have_BankInterleave_Item X_Ct_Retable_Auto proc near push di ; Save DI (Buffer) ;-------------------------------; ; Redirect Auto Table To 100MHz ; ;-------------------------------; mov si,offset Auto_CPU_66MHz ; Assign 66MHz DRAM Tbl call X_If_100MHz_DRAM_Clock jnc short Not_100MHz_DRAM_Clock_ mov si,offset Auto_CPU_100MHz ; Assign 100MHz DRAM Tbl Not_100MHz_DRAM_Clock_: mov di,si ; Save SI point, DI = SI mov bl,6 ;Bank 6/7 mov si, offset Bank_67_DRAM_Timing_Item ;Bank 6/7 call Prg_Auto_DRAM_Timing ;Bank 6/7 mov bl,4 ;Bank 4/5 mov si, offset Bank_45_DRAM_Timing_Item ;Bank 4/5 call Prg_Auto_DRAM_Timing ;Bank 4/5 mov bl,2 ;Bank 2/3 mov si, offset Bank_23_DRAM_Timing_Item ;Bank 2/3 call Prg_Auto_DRAM_Timing ;Bank 2/3 mov bl,0 ;Bank 0/1 mov si, offset Bank_01_DRAM_Timing_Item ;Bank 0/1 call Prg_Auto_DRAM_Timing ;Bank 0/1 pop di ; Restore DI (Buffer) ret X_Ct_Retable_Auto endp ;[]==============================================================[] ; Prg_Auto_DRAM_Timing: ; Programing Auto DRAM Timing ; ; Input : BL : Which bank is ? ; SI : SETUP Item Index of this bank ; DI : the SI of Ct_Retable_Auto ; Output : None ; Destory: EAX,DX,CX,BX,SI ;[]==============================================================[] Prg_Auto_DRAM_Timing Proc Near F000_call GetItem_Value ;What is Auto set ? test al,0FEh mov si,di ; Restore SI jnz short Not_Auto_DRAM_Timing or al,al ;if 60ns jz short Is_70ns ;No,jmp 70ns Is_60ns: add si, _DIFF1 ;assign 60ns table Is_70ns: mov cx, VT692 + 60h call X_Get_Ct mov cl,bl shr ax,cl and al,03h ifdef DEBUG_Auto_Timing out 9eh,al endif; DEBUG_Auto_Timing ; or al,al ;if Fast Page jz short Retable_Auto_Exit ;Yes, jmp ifdef Have_Fast_Page_DRAM_Table add si, _DIFF2 ;assign EDO table endif; Have_Fast_Page_DRAM_Table dec al ;if EDO jz short Retable_Auto_Exit ;Yes, jmp ifdef SUPPORT_SDRAM_II add si, _DIFF2 ;assign Burst EDO table dec al ;if Burst EDO jz short Retable_Auto_Exit ;Yes, jmp endif; SUPPORT_SDRAM_II add si, _DIFF2 ;assign SDRAM table jmp short Retable_Auto_Exit ; jmp Not_Auto_DRAM_Timing: push si ;because programing in cfeature.asm sub al,2 mov bh,al ; BH = DRAM Timing Item Set ; 0 = Normal ; 1 = Medium ; 2 = Fast ; 3 = Turbo mov cx, VT692 + 60h call X_Get_Ct mov cl,bl push bx ; Save BL value shr ax,cl and al,03h ; AL : bit 1-0 ; Detect the slowest of ; DRAM Type ; 00 : Fast Page ; 01 : EDO ; 10 : Burst EDO ; 11 : SDRAM mov bl,bh ; BX = DRAM Timing Item Set xor bh,bh ; 0 = Normal ; 1 = Medium ; 2 = Fast ; 3 = Turbo mov si,0 mov ah,0ffh ; FP & EDO RomRegMask or al,al ; SI = 0 (Fast Page) jz short @f ifdef Have_Fast_Page_DRAM_Table mov si,4 ; SI = 4 (EDO) endif; Have_Fast_Page_DRAM_Table dec al jz short @f mov ah,0CCh ; SDRAM RomRegMask ifdef SUPPORT_SDRAM_II IFDEF Have_Fast_Page_DRAM_Table mov si,8 ; SI = 8 (SDRAM II) ELSE; Have_Fast_Page_DRAM_Table mov si,4 ; SI = 4 (SDRAM II) ENDIF;Have_Fast_Page_DRAM_Table dec al jz short @f IFDEF Have_Fast_Page_DRAM_Table mov si,12 ; SI =12 (SDRAM) ELSE; Have_Fast_Page_DRAM_Table mov si,8 ; SI = 8 (SDRAM) ENDIF;Have_Fast_Page_DRAM_Table else; SUPPORT_SDRAM_II IFDEF Have_Fast_Page_DRAM_Table mov si,8 ; SI = 8 (SDRAM) ELSE; Have_Fast_Page_DRAM_Table mov si,4 ; SI = 4 (SDRAM) ENDIF;Have_Fast_Page_DRAM_Table endif; SUPPORT_SDRAM_II @@: add si, bx ; add DRAM Timing Item Set pop bx ; Restore BL value call Convert_DRAM_Table ; Convert SI to 100MHz DRAM Tbl ifdef DEBUG_Auto_Timing_1 push ax mov ax,si out 80h,al in al,9eh inc al out 9eh,al pop ax endif; DEBUG_Auto_Timing_1 mov al, byte ptr cs:[si+offset FP_DRAM_Tbl] pop si jmp short Program_Register Retable_Auto_Exit: ;-----------------------; ; Program Register ; ;-----------------------; push ds ; mov ax,DGROUP ; mov ds,ax ; Assume DS:DGROUP ; push si ; mov si,DS:[si] ; mov al,byte ptr DS:[si].RomValue ; Get AUTO Timing Tbl mov ah,byte ptr DS:[si].RomRegMask ; Get AUTO Timing Tbl ifdef DEBUG_Auto_Timing ; Setting Values out 80h,al ; endif; DEBUG_Auto_Timing ; pop si ; pop ds ; Program_Register: ifdef VCM_Support ;R37 call Transfer_VCM_Timing ;R37 endif; VCM_Support ;R37 mov cx, VT692 + 64h ; Programing DRAM Timing shr bl,1 ; BL=06 : Set Rx67h add cl,bl ; BL=04 : Set Rx66h mov bx,ax ; BL=02 : Set Rx65h call X_Get_Ct ; BL=00 : Set Rx64h and bl, bh not bh and al, bh or al, bl call X_Set_Ct ret Prg_Auto_DRAM_Timing Endp ;R37 - starts ifdef VCM_Support ;[]==============================================================[] ; Transfer_VCM_Timing: ; If Virtual Channel SDRAM (VCM), Set 5T for Prechange Command. ; ; Input : BL : Bank num, AX : Old DRAM Timing ; BL=06 : Bank 6/7 ; BL=04 : Bank 4/5 ; BL=02 : Bank 2/3 ; BL=00 : Bank 0/1 ; Output : AX : chang VCM Timing in AX register ; Destory: ;[]==============================================================[] Transfer_VCM_Timing Proc Near push bx shr bl,1 ; BL=03 : Get Bank 6/7 ; BL=02 : Get Bank 4/5 ; BL=01 : Get Bank 2/3 ; BL=00 : Get Bank 0/1 call X_Test_VCM ; Test If this bank support VCM ? jnz short Not_VCM_T and al,not 40h ; Set 5T for Prechange Command and ah,not 04h ; Don't Set RAS to CAS Time! Not_VCM_T: pop bx ret Transfer_VCM_Timing Endp ;[]==============================================================[] ; X_Test_VCM: ; If Virtual Channel SDRAM in this bank. ; ; Input : BL : Bank num, AX : Old DRAM Timing ; BL=03 : Bank 6/7 ; BL=02 : Bank 4/5 ; BL=01 : Bank 2/3 ; BL=00 : Bank 0/1 ; Output : ZE : Is VCM ; NZ : Not VCM ; Destory: Zero flag ;[]==============================================================[] X_Test_VCM Proc Near pushad push bx mov cx, VT692 + 58h ; Get Bank0/1/2/3 MA Type call X_Get_Ct ; mov bh,al mov cx, VT692 + 59h ; Get Bank4/5/6/7 MA Type call X_Get_Ct ; mov bl,al pop cx ; CL=03 : Get Bank 6/7 ; CL=02 : Get Bank 4/5 ; CL=01 : Get Bank 2/3 ; CL=00 : Get Bank 0/1 shl cl,2 mov ax,1000h shr ax,cl not bx and bx,ax popad ret X_Test_VCM Endp endif; VCM_Support ;R37 - ends ;[]==============================================================[] ; Convert_DRAM_Table: ; Convert DRAM Timing table to DRAM Timing table ; according to DRAM clock(66M/100M). ; ; Input : SI : the index of DRAM table ; Output : SI : the index of DRAM table ; Destory: Flag ;[]==============================================================[] Convert_DRAM_Table Proc Near call X_If_100MHz_DRAM_Clock jnc short Not_100MHz_DRAM_Clock add si,DRAM_Tbl_Offset ; Assign 100MHz DRAM Tbl Not_100MHz_DRAM_Clock: ret Convert_DRAM_Table Endp ;[]==============================================================[] ; X_If_100MHz_DRAM_Clock: ; Check If 100MHz DRAM Clock ? ; Input : None. ; ; Output : CY : Is 100MHz DRAM Clock ; NC : Not 100MHz DRAM Clock ; Destory: Flag, ;[]==============================================================[] Public X_If_100MHz_DRAM_Clock X_If_100MHz_DRAM_Clock Proc Near pushad ;R38 - starts call X_If_693A jb Not_693A ; Not 133Mhz Support ! call X_Measure_SDRAM_Speed cmp al,66 jz short Not_100MHz_ stc popad ret Not_693A: ;R38 - ends mov cx, VT692 + 69h ; See DRAM Clock call X_Get_Ct test al,80h ; 0 : 100/66 (CPU Clock) ; 1 : 66 (AGP Clock) jnz short Not_100MHz_ Post_func_Call Ct_Quatify_100Mhz ; If 100MHz Host CLK ? jnc short Not_100MHz_ ; stc popad ret Not_100MHz_: clc popad ret X_If_100MHz_DRAM_Clock Endp ;-----------------------; ; 692 DRAM Table ; ;-----------------------; ;>> 66MHz <<; FP_DRAM_Tbl: FP_DRAM_Tbl_66: ifdef Have_Fast_Page_DRAM_Table db 0D6h ;normal FastPage db 014h ;medium db 004h ;fast db 000h ;turbo endif; Have_Fast_Page_DRAM_Table EDO_DRAM_Tbl: EDO_DRAM_Tbl_66: db 0D6h ;normal EDO db 014h ;medium db 004h ;fast db 000h ;turbo ifdef SUPPORT_SDRAM_II SDRAMII_DRAM_Tbl: SDRAMII_DRAM_Tbl_66: db 0C4h ;normal 11xx01xxb SDRAM II db 0C4h ;medium 11xx01xxb db 040h ;fast 01xx00xxb db 040h ;turbo 01xx00xxb endif; SUPPORT_SDRAM_II SDRAM_Tbl: SDRAM_Tbl_66: db 0C4h ;normal 11xx01xxb SDRAM db 0C4h ;medium 11xx01xxb db 040h ;fast 01xx00xxb db 040h ;turbo 01xx00xxb DRAM_Tbl_Offset EQU $ - FP_DRAM_Tbl ;>> 100MHz <<; FP_DRAM_Tbl_100: ifdef Have_Fast_Page_DRAM_Table db 0EEh ;normal FastPage db 0DEh ;medium db 054h ;fast db 004h ;turbo endif; Have_Fast_Page_DRAM_Table EDO_DRAM_Tbl_100: db 0EEh ;normal EDO db 0DEh ;medium db 054h ;fast db 004h ;turbo ifdef SUPPORT_SDRAM_II SDRAMII_DRAM_Tbl_100: db 0C4h ;normal 11xx01xxb SDRAM II db 0C4h ;medium 11xx01xxb db 040h ;fast 01xx00xxb db 040h ;turbo 01xx00xxb endif; SUPPORT_SDRAM_II SDRAM_Tbl_100: db 0C4h ;normal 11xx01xxb SDRAM db 0C4h ;medium 11xx01xxb db 040h ;fast 01xx00xxb db 040h ;turbo 01xx00xxb if SENSOR_IN_CFEATURE ;R27 ifdef SENSOR_IN_XGROUP ;R27 include sensor.e8 ;R27 endif ;SENSOR_IN_XGROUP ;R27 endif; SENSOR_IN_CFEATURE ;R27 XCODE ENDS END