; []===========================================================[] ; ; NOTICE: THIS PROGRAM BELONGS TO AWARD SOFTWARE INTERNATIONAL(R) ; INC. IT IS CONSIDERED A TRADE SECRET AND IS NOT TO BE ; DIVULGED OR USED BY PARTIES WHO HAVE NOT RECEIVED ; WRITTEN AUTHORIZATION FROM THE OWNER. ; ; []===========================================================[] ; ;---------------------------------------------------------------------------- ;Rev Date Name Description ;---------------------------------------------------------------------------- ;R164 04/29/99 STV Fixed SCSI boot fail when use a ISA AHA-SCSI card. ; This reason is INT19 be replaced by the SCSI card and ; cause 'Enable_SCSI_Boot' flag not be enabled in int 19h. ; So we set this flag in POST instead int 19h. ;R163 03/17/99 KVN Added a short delay (1/8 second) after TCAV for fixed ; some mothermoard bug.This problem occrued on following ; enviroment: ; 1. SiS-620 chipset (2A6iNE19) ; 2. CPU runing at 266 MHZ or higher ; 3. Trend anti-virus function enabled ; 4. BIOS should use Flash ROM (not occur on ROM-emulate) ;R162 03/09/99 RCH 1. Added Boot from LAN devices with Bootstrap Entry ; Vector (BEV) boot ROM support. ; 2. Fixed BIOS can not boot from Intel/559 boot ROM ; if the PnP/BEV Boot is enabled. ;R146A 02/03/99 MIL Added Cyrix Cx5540 Chipset PCI_RESET SUPPORT. ;R161 01/22/99 TNY Clear esp high word to prevent system hang if ; emm386.exe installed. ;R160 01/14/99 MCH Rewrite the reset method as ZIDA's specification & ; Delete the stub/repeated define in R132. ;R159 12/02/98 KVN Fixed Pioneer DVD boot fail.The DVD model is ; [Pioneer DVD-ROM ATAPIMOdel DVD-A02X 0105] ;R121H 11/19/98 RIC If not define "No_Cut_IRQ12_When_No_PS2_Pluged" ; ,force define "Disable_VIA_PS2_In_PCI_RESET" to make ; system be stable in PCI Reset. ;R158 11/19/98 PHI Patch that the VGA BIOS shadow RAM of ET4000/W32P ; isn't protected after the VGA BIOS execution. ; The causation is that the VGA BIOS destroy BP register ; and cause the system BIOS get invalid data reference. ;R121G 11/17/98 RIC Add "Disable_VIA_PS2_In_PCI_RESET" for VIA_PCI_Reset ; to fix system hang at PCI Reset in SMC I/O chip. ;R125C 11/11/98 RCH Support pressing Hotkey to force boot to network ; before booting from local storages. For example, ; "HOTKEY_TO_BOOT_LAN EQU 058H" use function key F12 to ; force boot to LAN. ;R125B 11/10/98 RCH Fixed system can not boot back to normal devices when ; boot failed from LAN if the user enable ; "Boot from LAN first" and the LAN boot ROM trap both ; INT 18H & 19H. We saw the problem on Winboard PCI/LAN ; boot ROM. ;R157A 10/26/98 MCH Update the Gemlight MBI Structure from v1.0 to v1.01. ;R157 10/20/98 MCH Added Gemlight M/B Info area for Gemlight customer ;R156 10/12/98 KVN Added Int 18h handler return to Int19h feature to fixed ; HDLOCK tool work correctly.That is don't check active ; flag for HDD.If HDD boot fail in master sector then it ; will call Int 18h so we return to int 19h at this time. ;R155 10/03/98 KVN Fixed execute ZDIAG.EXE test program of CPU test item ; then cause system hang.That reason is BIOS not reset ; SS:SP if test program issue shutdown then BIOS will ; destroy memory content of SS:SP pointed ;R154 10/01/98 TNY Problem: ; PIIX4 will launch 62us pulse when pci reset ; launched then cause HDD read/write error if some ; bad power-supply plugged. ; Sloution: ; Add a long delay cycle before pic reset to ; wait HDD read/write finished. ;R153 09/29/98 KVN Release DMI and ESCD pool in flash ROM when not define ; "ESCD_SUPPORT" and "FLASH_SUPPORT" in BIOS.CFG ;R152 09/09/98 BAR Added a define does not check HDD active bit. ; "No_Check_HDD_Active_Bit EQU 1 " ;M01 09/02/98 RAY Adapt Preboot-Agent from code modified by US ; (01/29/98 TJM) Added MPC 2.0 (Formerly RPB) modifications ; ;R151 08/25/98 RAY Add definition: "Special_Before_INT19" for ; customization in which you have to add routine ; Ct_Before_INT19 in CHIPPOST.ASM ;R150 08/11/98 KVN Added "request sense command" to exactly report ATAPI ; access status.That will dont delay or loop for some ; boot fail CDROM ;R149 07/27/98 KVN Add a new boot sequence 'A,CDROM,C' for choise.If you ; want to use it.You should define 'BOOT_FORM_A_CD_C' in ; BIOS.CFG ;R148 07/09/98 JSN Add No_Save_Warm_Boot_Flag defination for some manufacturer ; request. ;R141A 06/17/98 KVN Modify some code for TCAV v1.62 ;R147 06/11/98 KEN Set the default value of USB_STATUS to be USB disabled, ; avoid abnormal action in SMI routine between the SMI ; initialization and USB initialization. ;R146 06/09/98 MIL Added Cyrix Cx5530 Chipset PCI_RESET SUPPORT. ;R126B 06/08/98 AVN Change 'SIS_5591_PCI_RESET' to 'SIS_5595_PCI_RESET' ; for SiS5591 and SiS5600 use SiS5595 (same pci isa bus) ;R145 06/05/98 MAX Support CMOS default value save to 2M ROM Flash function ;R144 05/27/98 TNY Fix Intel 82558 RPL bootrom (Novell) V1.00(940810) ; boot failure. Just (AND DL,NOT 80H) is OK. ;R143 05/21/98 DNL Added memory usage report for ACPI BIOS to prevent ; "Unreported memory" for HCT 7.5 ;R142 05/12/98 TNY Added "Some_Delay_Before_PCIRESET" for 2a59fd29.cfg ; to fix hardware problem.(hang in PCIRESET sometime) ;R141 03/12/98 KVN Added ChipAwayVirus ROM to F000 shadow ;R140 03/10/98 DNL Reduce ACPI S4/BIOS code size to save more space ;R121F 03/05/98 RIC Add VIA 596 South Bridge chip Support. ; (Fixed that System can't reboot/PCI Reset) ;R138A 02/26/98 TNY Fix Toshiba 8MB EDO reset hang. ;R139 02/25/98 DNL Added ACPI S4/BIOS support ;R138 02/20/98 TNY Add 443BX reset collision with refresh followed ; BIOS spec update E1.(Option:PCI_RESET_FOR_443BX) ;R136A 02/11/98 KVN Fixed coding mistake ;R137 02/02/98 PAL Fixed error when shadow unit use 32k ;R136 01/19/98 KVN Fixed HDD boot fail if not set active bit.Now we will ; boot to next sequence if not found any active partition ; in HDD ;R125A 01/13/98 KVN Fixed coding mistake to destroy AX by R125 that will ; cause boot first always fail if boot from lan card but ; none lan chip or card on mother board ;R135 01/03/97 STV Fixed Mylex DAC960 RAID controller card cannot work ; successfully while the PS/2 mouse is not plugging, ; the card will set to disable automatically while ; without PS/2 mouse.PS/2 mouse plugging flag isn't ; config_table+5 ,so change to SYSTEM1_BYTE(bit 2). ; Config_Table+5 is EBDA flag. See atorgs.asm ;R132A 12/20/97 MIL Add definition: SPECIAL_ISSUE_SYSTEM_RESET ; : ; Some chipset have no PCI_RESET_SUPPORT, so we can ; add a hook to reset some onboard chip, during system ; warm boot. About the code format ,please follow R132. ; ; ;R134 12/17/97 JSN Support ALADDIN 5 PCI hardware reset. ;R123D 12/15/97 BAR added detect pioneer 24x cdrom try more times. ; "Pioneer CD-ROM ATAPI Model DR-A24X 0102" ; Load data from shadow RAM 'CDROM_Boot_Delay' ;R133 12/08/97 DNL Added ACPI on/off option support ;R132 12/06/97 RAY Add definition: SPECIAL_ISSUE_SYSTEM_RESET ; ; If any chipset has a special design to reset the ; system, please add this definition in BIOS.CFG & ; add hook "Ct_Issue_System_Reset" in CHIPRUN.ASM. ; ; The purpose of this hook to let engineers to add ; customization codes in chipset dependent files but ; not in ATBASE.ASM ! ; ;R131 12/06/97 MIL Added "Gx86_VSA_Final_Init" function before INT 19h. ;R130 12/05/97 PAL Added Trend_AntiVirus Support by Cbrom / vrs ;R121E 12/02/97 RIC Add a forever loop after PCI Reset routing to make system ; be stable. (VIA chip). ;R123C 11/27/97 STV Fixed some bootable CD diskette (from FIC) boot failure. ; The reason is our BIOS access CD use head is 16.So BIOS ; accessable maximum size is 1024*16*63 sectors(about 528MB) ; and CD diskette total space is large than 640MB.If data ; in CD are locate over 528MB then BIOS can not access it. ; Now we increase default head number to 255 for support ; access to 8.4GB ;R123B 11/26/97 BAR Fixed CD-ROM CDU571 can't boot ;R126A 11/10/97 AVN Fixed SiS 5591 pci reset to correct way. ;R129 11/07/97 RAY Kill some un-used external definitions ;R128A 11/04/97 RCH Fixed error coding for R128 ;R121D 10/29/97 AVN Saving SiS5598 F000h Segment Code. ;R128 10/29/97 RCH Fixed system sometimes have no display if VGA's RAM ; is SGRAM while PCI reset is issued. ;R127 10/24/97 BAR Fixed boot sequence CD_ROM frist very slow ; if media is audio CD or can't bootable. ; This CDROM model list follow: ; Panasonic "MATSHITA CR_585" ;R123A 10/23/97 KVN Fixed CD-ROM CDU511 can't boot if connect it on slave ;R126 10/14/97 LAW Added SiS5591 PCI reset support ;R111B 10/09/97 RIC Fixed that OS/2 hang when BIOS define "ACPI_Support". ;R125 10/07/97 RCH Added boot from LAN option support ;R121C 10/06/97 AVN Fixed still hang in some custom like JETWAY when use ; AMD K6 166MHz. ;R121B 09/19/97 AVN Added PCI reset more delay time for SIS 5598, because ; still hang in some custom like JETWAY. ;R124 08/22/97 AVN Fixed SiS5598 with windows Memphis 98 cannot restart ; for gemlight, define 'Specail_align_for_Memphis98' ;R111A 08/08/97 DNL Fixed E820h function report error while memory hole enable ;R123 08/08/97 BAR Fixed CD-ROM CDU511 can't boot ;R122 08/05/97 RCH Added special diskette booting signature checking ;R121A 07/07/97 JKY Added PCI reset delay time for SIS_5598_PCI_RESET define ;R121 07/02/97 AVN Added SiS5598 PCI reset support, and rewrite PCI reset ; code for more readable. ;R116C 06/27/97 RCH The patch for SiS5571 is done by chipset dependent ; file(chippost.asm). ;R102C 06/24/97 RIC Add code to judge if VIA chip support PCI_RESET ? ;R116B 06/23/97 RCH Fixed system resource conflict if USB controller is ; enabled and Trident 9685 VGA card is plugged for ; SiS5571 ;R120 06/13/97 KVN Support DriveA_Boot_Permit function by setup option ;r119 06/04/97 PTY Add code for RPB ;R118 05/29/97 KVN Added a new segment for store more BIOS code ;R116A 05/08/97 RCH The "unreport memory error" is caused by wrong memory ; sizing, kill the un-necessary code ;R115A 05/07/97 KVN Add ZIP100 bootable same as LS120 ;R117 05/05/97 KVN Fix CDROM boot fail if system is SCO and emulate to floppy ;R116 05/02/97 RCH Added patch code to pass SCT test for M/B's not ; decode memory space properly. It's not a good idea ; but customer don't want to fix the hardware. ;R102B 05/02/97 RIC VIA 586B(ACPI) F version or later must clear ; VT586_ACPI+41h bit 7 before PCI RESET. ;R115 05/01/97 KVN Add LS120 bootable even floppy A exist ;R102A 05/01/97 RIC VIA 586B(ACPI) F version don't support PCI_RESET ;R113A 04/29/97 RAY The SW SMI issued for the VSA to finalize their own ; configuration should be moved from ATBASE.ASM before ; "INT 19h" to the chipset dependent routine: PM_FINAL_INIT ; in PMUPOST.ASM . This is somehow related to ECS's board ; which cannot boot up after ESCD is updated successfully ! ;R114 04/18/97 KVN Added MP table for dynamic to built into shadow ;R113 04/01/97 KVN Added some code for Cyrix Gx86 & Cx5510 ;R112 03/31/97 JSN Added ALiM153x_Hardware_RESET define. ;R111 03/03/97 KVN Added ACPI function support ;R110 02/20/97 KVN Add "A,CDROM,SCSI" and "C,CDROM,SCSI" 2 item choise ; for WINCOM customer when define "WINCOM_boot_item" switch ;R109A 01/24/97 AVN Fixed if dual CPU board and only single CPU plug will ; hang at wait CPU2 init ;R109 01/24/97 AVN Fixed if CPU2 ID match in CPUCODE.ASM and time is not ; enough to update micro code at sometime. ;R108 01/22/97 RAY Use 8000h as temp address for initializing the second ; CPU which is confict with the new architechure of ; decompressing combined stuffs. ; ; Note: 8000h is defined in COMMON.EQU as ; "CPU2_SEGMENT EQU 8000h" ; ;R107 01/22/97 RAY Delete the unnecessary codes ;R106 01/14/97 RCH Temporary patch for MP with 5 PCI slots ;R105 01/10/97 RCH Report correct L2 cache size for multiple Klamath ; CPU platform due to the cache is initiated just after ; INIT_MTRR , the old code is too early to read L2 size. ;R101A 01/09/97 KVN Cancel "No_Support_HiScan" parameter define for auto ; support EMM386.EXE 'HIGHSCAN' ;R104 12/24/96 AVN Support MP Secondary Update Code For 1M/2M EEPROM ;R103 12/05/96 RAY Do not try to issue any command to change the SMBASE ; of the second CPU if there is only one CPU installed. ; If we do so, it will cause this commnad left on the ; APIC bus waiting for response and thus decrease the ; performance a little bit. ;R102 11/25/96 RIC Support special PCI reset for VIA/VT680 chipset ;R101 11/25/96 KVN Ignore EMM386.EXE 'HIGHSCAN' parameter even added in ; config.sys ;R98A 11/19/96 KVN Fixed R98 cause CD boot NT4.0 can't install to SCSI ;R100 11/14/96 AVN Fixed Pass for AMIDIAG.EXE PnP BIOS test. ;R99 11/09/96 RCH BESTKEY+PS2 MOUSE+PENTUM 133Mhz cause installing ; WIN v3.11 sometimes hang up. ;R98 11/06/96 KVN Fixed some PCMCIA ROM card emulate boot to C error ;R97 11/01/96 KVN Added LS-120 support ;R96 10/21/96 KVN Fixed Toshiba CDROM (Model:XM-5522B booting failure if ; POST too fast ;R95 10/18/96 KEN Added F0DATA_DT for F000 descriptor as data segment. ;R94 10/17/96 DNL Added "E000_SMI_SUPPORT" definition to save F-segment ;R88A 10/16/96 KVN Fixed error of R88,this will cause don,t boot from A: ; when boot sequence chose "SCSI,A,C" but no SCSI drive ;R93A 10/16/96 STV Support only C boot be standard function ;R93 10/14/96 KVN Added "support_only_C_boot" definition for support only ; drive C boot ;R91A 10/11/96 RCH Fixed error coding of R91 , this will lose warm boot ; flag and only detect one CPU for MP system while ; warm booting ;R84A 10/09/96 RAY Problem in P5 Multi-P system: ; Sometimes fail to detect the 2nd CPU ; Solution: ; Change SMbase for the 2nd CPU after invoking. ;R92 10/08/96 KEN Add label USB_STATUS to record "USB Keyboard Support" ; enabled/disabled status. ;R91 10/08/96 RCH Fixed some 430HX M/Bs can not issue system reset ;R90A 10/05/96 RIC Lose external define. ;R90 10/04/96 RCH Rewrite routine Do_F000_Shadow to save codes ;R89 10/04/96 RCH Add SMI support for P6 multi-processor system ;R88 10/04/96 KVN Added boot HDD selectable function ;R81A 09/26/96 KVN Fixed R81 cause SCSI HDD can't boot because it is ; always replace INT 13h even no bootable CD ;R87 09/26/96 LRY 'Skip_HDD_Type_1_To_46', removed HD type table ;R86 09/24/96 RAY Fix P6 Multi-Processor system cannot boot from ; SCO-Unix: ; ; Change the Bus no. for PCI bus & ISA bus from ; 1-->0 & 0-->1 in the MP-table ; ;R85A 09/24/96 KEN Fixed coding mistake. ;R85 09/23/96 RCH Program local & I/O APIC ID to get proper non-conflict ; ID for P6 MP system. ;R84 09/20/96 RAY Add SMI support for 586 multi-processor system ;R83 09/20/96 KEN Add label USB_RAM_SEG for supporting USB_RAM with ; shadow RAM. ;R82 09/17/96 RCH Change memory size report method to get memory hole ; size table for function E820H ;R81 09/17/96 KVN Add bootable CDROM no emulation support for NT 4.0 ;R80 09/07/96 RCH Move part of codes to ATORGS.ASM to save F-segment ; space ;R79 09/03/96 RCH Get boot sequence from BIOS data area instead of ; reading CMOS value ;R78 08/17/96 JASON No mesage when boot from CD_ROM ;R77A 07/11/96 RCH Should qualify E000_USED_BY_PCI due to non-PCI system ; otherwise compile failure ;R77 07/05/96 RAY In PCIPOST.ASM, we release the E0000-E7FFF shadow RAM ; for PCI ROM. ; ; If this area is assigned for PCI ROM, the E shadow ; cannot be disabled any more. ; ; Also, we have to clear the shadow RAM according to ; the shadow RAM used in order that the EMM386 can use ; this area as UMB. In PCIPOST.ASM, it can only clear ; the RAM before E8000h. Therefore, we have to modify ; the routine PREINT_19(ATBASE.ASM) to kill code from ; E8000 onward (which originally responsible for ; clearing E0000-E7FFF) ; ;R76 07/02/96 RAY Modify the devnode reporting the EXT memory size ; according to SCT 5.10 ;R75 06/21/96 RCH Added a switch to scan option in E0000H while system ; BIOS only occupied 64K before booting ;R74 06/10/96 RCH Save both CPUIDs for DP system for INT 15H , function ; 0D042H to update P6 micro-code ;R73 06/07/96 RCH Don't build MP table entry 20,21 & 22 due to MPS test ; program failure for new IOAPIC ;R72 06/01/96 KVN Disable interrupt flag (CLI) to prevent SP or BP be ; destroy by any interrupt to fix system hang at POST_82S ; (80h port is 52h) sometimes ;R71 05/29/96 RCH Support special PCI reset for VLSI/LYNX chipset ;R70 05/23/96 RCH Record P6 L2 cache in temporary are for POST to show ; size ;R69 05/23/96 RCH Fixed system shutdown hang for P6/MP under NT 3.51 ; server version. ;R68 05/10/96 KVN Don't display CDROM model at CDROM booting.because POST ; already show it ;R67 05/09/96 RCH Support PCI reset function for warm boot by using ; I/O 0CF9H to reset system. ;R66 05/07/96 KVN Fixed still display CDROM boot message if CDROM boot ; not be selected(i.e. BootSeq_Item value below 2) ;R65A 05/02/96 DNL Fixed coding mistake ;R65 04/23/96 DNL Added codes for Notebook Power Management ;R64A 04/18/96 RCH Fixed NT can not 2 P6 CPUs for Natoma DP system ;R64 03/26/96 RCH Added extra table for INTEL new APIC chip for PCI ; interrupt routing of MP table ;R63 03/21/96 KVN Support Floppy B drive bootable when drive A is error ; (use software swap floppy function) ;R62 03/04/96 RCH Disable MP table and local APIC initial if no IO APIC ; installed for P6 system. This can use the same BIOS ; to support both MP and Non-MP M/B. ;R61 02/13/96 KVN Fixed BIOS hang at 0C5h when old versio only shadowed ; E8000h-EFFFFh then update new version BIOS ;R60 01/30/96 KVN Ignore floppy boot sequence if floppy A type is none ; and INT13/INT40 not redirect ;R59 01/20/96 RCH Move the MP table to here , because it can be located ; at any where in 0E0000-FFFFF. ;R58 01/19/96 RCH Fixed P6 CPU can not execute NMI handler while the ; local APIC is enabled.according to MP v1.4 spec. ;R57 01/18/96 RCH Fixed system can not boot from CD-ROM if there is only ; one SCSI hard drive installed. ;R56A 01/15/96 KEN Reserve original updating ESCD method. ;R56 01/12/96 KEN Support updating ESCD with high memory (below 4GB). ;R55 01/10/96 RCH IBM real time coprocessor interface card always use ; E0000-EFFFF area, BIOS have to disable shadow and ; ROMCS# of this region. ;R50A 12/15/95 KVN Added "AVIDEO_AT_F000" option for Release full E000 segment ;R54 12/04/95 KVN Fixed system hang if run AZTECH sound card on VIA mother ; board ;R51A 11/28/95 RCH "Init_Mtrr" only available for P6 CPUs ;R53 11/22/95 KVN Fixed OAK 6x CD-ROM accerr error ;R52A 11/16/95 KVN Fixed R52 error ;R52 11/15/95 KVN Fixed GCD-R520B CD-ROM can't boot ;R51 11/09/95 RCH BIOS have to initial MTRR for all P6 CPUs , the BSP ; is programmed in POST , the AP CPUs are programmed ; here. ;R49A 11/07/95 RCH The P6 local APIC is different with P6, so don't read ; ID for P5 ;R50 11/01/95 KVN Release full E000 segment size for none PNP bios ;R49 11/01/95 RCH The local APIC ID for P6/MP system is not zero for ; BSP, so BIOS have to modify the local APIC ID in MP ; table, otherwise system can not boot from NT ;R48 10/21/95 RCH Change MP detection method for P6 , I don't know ; this method is workable for P5 or not, so use ifdef ; to select different codes for P5 & P6 ;R47 08/24/95 KVN Adjust E000 segment start offset at 0 ;R46 08/22/95 RCH Move GDT table from pcipost.asm to atbase.asm ;R44A 08/04/95 KVN Fixed CD_ROM can't boot because R44 ;R40A 08/03/95 RAY No_Support_4_IDE should placed after "include bios.cfg" ;R45 07/21/95 KVN Added HDD access AUTO mode ;R44 07/18/95 KVN Clear E000h shadow before call int 19h for emm386.exe ;R42A 07/17/95 KVN Fixed HDD CHS/LBA/LRG mode auto set function bug when ; not support 4 drive ;R43 07/11/95 KVN Added CD-ROM multi bootable function ;R42 07/08/95 KVN Added HDD CHS/LBA/LRG mode auto set function ;R41 06/15/95 KVN Fixed HDD can't boot if only 1 drive and bios include ; CD-ROM bootable drive ;R40 06/14/95 KVN Open Support_4_IDE feature become standard feature ;R39 06/13/95 KVN Reduce Post_func_call and F000_call code size ;R38 06/12/95 DNL Modify some codes to save more registers value ;R37 05/30/95 KVN Add display CD-ROM Model Number string ;R36 05/25/95 KVN Move MP POST codes from MULTISER.ASM ;R35 05/19/95 DNL Modify some codes to save more registers value ;R26A 05/12/95 KVN Fix R26 mistake ;R28 05/08/95 KVN Add CD-ROM bootable feature ;R27A 04/20/95 RCH Fixed error coding of R27 ;R27 04/11/95 RCH Fixed OS2 intstallation failure if PS2 mouse not plug ;R26 03/30/95 KVN Fix HDD parameter wrong when drive1 is absent ;R25 03/28/95 RCH Set PARA instead of DWORD to make aligment available ;R24 03/18/95 RCH Pass PCI bus,device & function information for video ; ROM intialiation for PCI/VGA ;emultiser.asm ;R23 09/10/94 RCH Move power on codes from atbase.asm to multiser.asm ;R22A 09/10/94 RCH Let override function be non-standard . ;R22 09/06/94 RAY Add No_Override_Key Option ;R21 07/09/94 RCH Upgrade EISA BIOS into v4.50G ;R20 07/06/94 RCH Added MP(Multi-processor) support ;R19 06/02/94 KVN Support 4 IDEs ;R18 05/24/94 RCH Give up some unused codes ;R17 05/20/94 KVN Open IDE LBA MODE function. ;R16 04/28/94 KVN Added IDE Logical Block Address (LBA) mode. ;R15 04/22/94 DNL Don't check AMD CPU SMI occured or not if system warm boot ;R14B 04/18/94 RAY R14 becomes invlid ;R14A 03/21/94 RAY Ct_Restore_Cyrix_Reg ;R14 03/19/94 RAY Lock Cyrix registers after restoring ;R13 03/19/94 RAY Don't include .EXT files any more ;R12 03/10/94 RCH Changed POST stack from 0FFFH to 1000H, because the ; Adaptec/7870 adaptor ROM can not accept odd stack ;R11 03/04/94 DNL Reinit IBM CPU register druing CPU reset. ;R10 03/01/94 KVN Fixed up PCMCIA drive can't boot when A drive is none. ;R09 02/21/94 DNL Fixed TI 486SXL2 CPU clock detection incorrect bug ;R08 02/05/94 KVN Referance atorgs.asm R19 ;R07 01/12/94 RAY Add AMD/U5 SMI support ;R06A 12/13/93 RCH Change some codes for CYRIX CPU for write back cache ;R06 09/15/93 DNL Restore CYRIX CPU register druing system shutdown ;R05 08/26/93 RCH Don't turn on cache except system shutdown occured ;R04 05/31/93 DNL Restore CPU CLOCK mode from G_RAM if warm boot ;R03 05/17/93 RAY Restore CPU type from G_RAM only if CMOS failure. ;R02 05/13/93 RAY Add Power Management for resuming ;R01 02/15/93 RCH Restore CPU type from G_RAM if warm boot PAGE 56,132 TITLE ATBASE -- 386 ROM/BIOS BASE .386P ;[]-----------------------------------[] ; ; Award Software 386/486 BIOS ; Base + Initialization Rtns ; Initial Revision 17-Apr-1990 ; ;[]-----------------------------------[] IDE_LBA_MODE_SUPPORT EQU 1 ;R17 ;R40A ifndef No_Support_4_IDE ;R40 ;R40A Support_4_IDE EQU 1 ;R40 ;R40A endif ;No_Support_4_IDE ;R40 .XLIST INCLUDE BIOS.CFG INCLUDE PNP.EQU ;R100 ;M01 - starts ifdef RPB_ENABLED include rpb.cfg endif ;RPB_ENABLED ;M01 - ends ifndef No_Support_4_IDE ;R40A Support_4_IDE EQU 1 ;R40A endif ;No_Support_4_IDE ;R40A ;R50A start ifndef PNP_BIOS AVIDEO_AT_F000 EQU 1 endif ;PNP_BIOS ;R50A end .list ;R141 INCLUDE COMMON.EQU INCLUDE POST.EQU ;R141 INCLUDE 8042.EQU ;R141 INCLUDE 8259.EQU ;R141 INCLUDE MATHCOP.EQU ;R141 INCLUDE CT_TABLE.EQU INCLUDE COMMON.MAC INCLUDE POST.MAC include cd_rom.equ ;R81 ;R13 INCLUDE ATORGS.EXT ;R13 INCLUDE CACHE.EXT ;R13 INCLUDE CHIPSET.EXT ;R13 INCLUDE CPU.EXT ;R12 ;R13 INCLUDE CT_TABLE.EXT ;R114ifdef MP_SUPPORT ;R51 ;R114ifdef P6_BIOS_ONLY ;R51A ;R114 extrn Init_Mtrr:near ;R51 ;R114endif; P6_BIOS_ONLY ;R51A ;R114 extrn If_MP_PLUGGED:Near ;R103 ;R114endif; MP_SUPPORT ;R51 ;R150 extrn WAIT_REFRESH:near ;R123A extrn HRDSKIO:far ;R57 extrn DSK_VECT:near ;R60 ifdef Trend_AntiVirus ;R130 extrn Open_PM_RAM:near ;R141 extrn Close_PM_RAM:near ;R141 ;R141 extrn Ct_Shadow_Unit:Near ;R137 ;R141 extrn Ct_Shadow_R:Near ;R130 endif; Trend_AntiVirus ;R130 ;R24 - start ifdef PCI_BUS ;Pass PCI parameters for ROM initialization extrn PCI_VGA_INFO:ABS endif; PCI_BUS ;R24 - end EXTRN CODE_END:NEAR ;R19 EXTRN INT_INITS:WORD ;R13 EXTRN SIZE_INT_INITS:ABS ;R13 EXTRN ENABLE_PARITY:NEAR ;R13 EXTRN GET_CMOS:NEAR ;R13 EXTRN SET_CMOS:NEAR ;R13 EXTRN FDC_PARS:BYTE ;R13 EXTRN INT18_HDLR:NEAR ;R13 ;R99 EXTRN BAD_DISK_MSG:BYTE ;R13 EXTRN WR_STR_TTY:NEAR ;R13 EXTRN DRV0:NEAR ;R13 EXTRN DRV1:NEAR ;R13 EXTRN DRV2:NEAR ;R13 EXTRN DRV3:NEAR ;R13 extrn HDDC_ITEM:Near extrn HDDD_ITEM:Near ifdef Support_4_IDE extrn HDDE_ITEM:Near extrn HDDF_ITEM:Near endif ;Support_4_IDE extrn Get_HDD_CMOS_Info:Near extrn Set_HDD_parm:Near extrn POST_func_end:Near extrn POST_VECT:Near EXTRN CPU_CACHE:NEAR ;R13 EXTRN CT_VERY_EARLY_INIT:NEAR ;R13 EXTRN SND_SPKR:NEAR ;R13 EXTRN SYS_INITS:WORD ;R13 EXTRN SIZE_SYS_INITS:ABS ;R13 ;R129 EXTRN PRG_CHIPSET_DEFAULT:NEAR ;R13 EXTRN BUFFER_8042_FULL:NEAR ;R13 EXTRN OUT_8042_FULL:NEAR ;R13 extrn Ct_Restore_Cyrix_Reg:Near ;R14A ;R21 - start IF BUS_TYPE EQ EISA_BUS extrn Ct_EISA_ID:near extrn EISA_MOTHERBOARD_ID:byte extrn Init_EISA_reg:near ENDIF ;BUS_TYPE ;R21 - end ;r1000 start ;R13 include akbrd.ext ;R141 include port61.equ ;r1000 end extrn POST_func_end:Near ;128k extrn POST_VECT:Near ;128k extrn Init_Cyrix_Reg:near ;R21 extrn IntCache_Item:near extrn Exc9hdlr:near extrn A20_On:near extrn Normal_Post_Tests:near EXTRN POST_3S:NEAR EXTRN POST_4S:NEAR EXTRN POST_5S:NEAR EXTRN POST_6S:NEAR EXTRN POST_7S:NEAR EXTRN POST_8S:NEAR EXTRN POST_9S:NEAR EXTRN POST_10S:NEAR EXTRN POST_11S:NEAR EXTRN POST_12S:NEAR EXTRN POST_13S:NEAR EXTRN POST_14S:NEAR EXTRN POST_15S:NEAR EXTRN POST_16S:NEAR EXTRN POST_17S:NEAR EXTRN POST_18S:NEAR EXTRN POST_19S:NEAR EXTRN POST_20S:NEAR EXTRN POST_21S:NEAR EXTRN POST_22S:NEAR EXTRN POST_23S:NEAR EXTRN POST_24S:NEAR EXTRN POST_25S:NEAR EXTRN POST_26S:NEAR EXTRN POST_27S:NEAR EXTRN POST_28S:NEAR EXTRN POST_29S:NEAR EXTRN POST_30S:NEAR EXTRN POST_48S:NEAR EXTRN POST_49S:NEAR EXTRN POST_50S:NEAR EXTRN POST_51S:NEAR EXTRN POST_52S:NEAR EXTRN POST_53S:NEAR EXTRN POST_54S:NEAR EXTRN POST_55S:NEAR EXTRN POST_56S:NEAR EXTRN POST_57S:NEAR EXTRN POST_58S:NEAR EXTRN POST_59S:NEAR EXTRN POST_60S:NEAR EXTRN POST_61S:NEAR EXTRN POST_62S:NEAR EXTRN POST_63S:NEAR EXTRN POST_64S:NEAR EXTRN POST_65S:NEAR EXTRN POST_66S:NEAR EXTRN POST_67S:NEAR EXTRN POST_68S:NEAR EXTRN POST_69S:NEAR EXTRN POST_70S:NEAR EXTRN POST_71S:NEAR EXTRN POST_72S:NEAR EXTRN POST_73S:NEAR EXTRN POST_74S:NEAR EXTRN POST_75S:NEAR EXTRN POST_76S:NEAR EXTRN POST_77S:NEAR EXTRN POST_78S:NEAR EXTRN POST_79S:NEAR EXTRN POST_80S:NEAR EXTRN POST_81S:NEAR EXTRN POST_82S:NEAR EXTRN POST_83S:NEAR EXTRN POST_84S:NEAR EXTRN POST_85S:NEAR EXTRN POST_86S:NEAR EXTRN POST_87S:NEAR EXTRN POST_88S:NEAR EXTRN POST_89S:NEAR EXTRN POST_90S:NEAR EXTRN POST_91S:NEAR EXTRN POST_92S:NEAR EXTRN POST_93S:NEAR EXTRN POST_94S:NEAR EXTRN POST_95S:NEAR EXTRN POST_96S:NEAR EXTRN POST_97S:NEAR EXTRN POST_98S:NEAR EXTRN POST_99S:NEAR ;R79 extrn BootSeq_Item:near ;R79 extrn GetItem_Cmos:near ;R79 extrn GetItem_Value:near ;R42 extrn Write_Item_Value:near ;R42 extrn HDD_TYPE_DIFF:ABS ;R42 extrn SYSTEM1_BYTE:near ;R135 ;r119 start ifdef RPB_ENABLED ;M01 extrn rpb_is_running:near ; RXX extrn rpb_f000_is_running:near ;M01 extrn rpb_set_dos_mode:near endif ; RPB_ENABLED ;r119 end ;M01 - starts ifdef RPB_BOOT_FAIL_TRIGGER extrn rpbf_preboot_agent_trigger:proc endif ;RPB_BOOT_FAIL_TRIGGER ;M01 - ends ;R02 start ifdef PM_SUPPORT extrn Ct_Resume_Handle:near extrn Ct_Sleep_Detect:near extrn Ct_Check_SMI_Start:Near ;R07 endif ;PM_SUPPORT ;R02 end ifdef IDE_LBA_MODE_SUPPORT ;R16 extrn Set_HDD_parm:Near ;R16 endif ;IDE_LBA_MODE_SUPPORT ;R16 ifdef QUERY_SYSTEM_ADDRESS_MAP extrn ExtData1Kb:Near extrn ExtMem128Mb:Near extrn MemHole_15Mb:near ;R82 extrn MemAbove_15Mb:near ;R82 extrn Ct_MemHole_Status:near ;R82 ;R111 start ifdef ACPI_Support extrn ACPITableAddress:near ;ACPI extrn ACPINVSAddress:near ;ACPI extrn ACPI_Memory:near ;R143 endif; ACPI_Support ;R111 end endif ;QUERY_SYSTEM_ADDRESS_MAP extrn CONFIG_TABLE:near ;R27 ;R44A extrn Auto_IDE_Detect:near ;R37 extrn Display_String:near ;R37 extrn E000_64K_shadow_RW:near ;R44 extrn E000_64K_shadow_R:near ;R44 extrn Disable_E000_ROM_Shadow:near ;R77 IF RELEASE_E000_FOR_PCI ;R77 ifdef PCI_BUS ;R77A extrn E000_USED_BY_PCI:near ;R77 endif; PCI_BUS ;R77A ENDIF ;RELEASE_E000_FOR_PCI ;R77 extrn cpu_halt:near ;R84 extrn Int13_original_address:dword ;R81A extrn SCSI_Drive_Max_Num:byte ;R88A ifdef E000_SMI_SUPPORT ;R94 extrn Restore_E000_Shadow_Status:FAR ;R94 endif ;E000_SMI_SUPPORT ;R94 ;R150 extrn CDROM_Boot_Delay:near ;R123D ;R150 extrn CDROM_Boot_loop:near ;R123D .LIST ;[]---------------------------[] ; ; Low memory init (1st 64k) ; ;[]---------------------------[] G_RAM SEGMENT USE16 AT 0 ORG 04H*4 INCLUDE SEG_0.INC ORG 400H INCLUDE G_RAM.INC ORG 7C00H BOOT LABEL FAR G_RAM ENDS ;[]---------------------------[] ; ; Stack init ; ;[]---------------------------[] BIOS_STK SEGMENT USE16 AT 0H ORG 400H BIOSSTK_TOP LABEL WORD IF1 %OUT USING 1000h POST STACK LOCATION ENDIF ORG 1000h POSTSTK_TOP LABEL WORD BIOS_STK ENDS PAGE DGROUP GROUP FCODE ;R25 FCODE SEGMENT USE16 DWORD PUBLIC 'CODE' FCODE SEGMENT USE16 PARA PUBLIC 'CODE' ;R25 ASSUME CS:dgroup,DS:dgroup ;R107 IFDEF S64K ;R107 IF1 ;R107 %OUT S64K flag set: ORG set to 0 for 64K BIOS ;R107 ENDIF ;R107 ORG 0 ;R107 ;R107 ELSEIFDEF S60K ;R107 IF1 ;R107 %OUT S60K flag set: ORG set to 1000h for 60K BIOS ;R107 ENDIF ;R107 ORG 1000h ;R107 ;R107 ELSEIFDEF S56K ;R107 IF1 ;R107 %OUT S56K flag set: ORG set to 2000h for 56K BIOS ;R107 ENDIF ;R107 ORG 2000h ;R107 ;R107 ELSEIFDEF S52K ;R107 IF1 ;R107 %OUT S52K flag set: ORG set to 3000h for 52K BIOS ;R107 ENDIF ;R107 ORG 3000h ;R107 ;R107 ELSEIFDEF S48K ;R107 IF1 ;R107 %OUT S48K flag set: ORG set to 4000h for 48K BIOS ;R107 ENDIF ;R107 ORG 4000h ;R107 ;R107 ELSEIFDEF S44K ;R107 IF1 ;R107 %OUT S44K flag set: ORG set to 5000h for 44K BIOS ;R107 ENDIF ;R107 ORG 5000h ;R107 ;R107 ELSEIFDEF S40K ;R107 IF1 ;R107 %OUT S40K flag set: ORG set to 6000h for 40K BIOS ;R107 ENDIF ;R107 ORG 06000H ;R107 ;R107 ELSEIFDEF S36K ;R107 if1 ;R107 %OUT S36K flag set: ORG set to 7000h for 36K BIOS ;R107 endif ;R107 ORG 07000H ; START OF ROM, DISK WHIZ ;R107 ;R107 ELSE ; S32K ;R107 IF1 ;R107 %OUT Default: ORG set to 8000h for 32K BIOS ;R107 ENDIF ;R107 ORG 08000H ; START OF ROM ;R107 ;R107 ENDIF ; SxxK PUBLIC CODE_START CODE_START: PAGE dw offset code_end ;R08 ;R101A;R101 start ;R101Aifdef No_Support_HiScan ;R101A public INT06_VECT ;R101AINT06_VECT: ;R101A extrn LOADALL:near ;R101A jmp LOADALL ;R101Aendif ;No_Support_HiScan ;R101A;R101 end ;R39 start public Post_call_proc Post_call_proc: push offset POST_func_end ;R118 push 0f000h push ax pushf ;R72 cli ;R72 xchg bp,sp ;R72 mov ax,[bp+2] ;R72 xchg ax,[bp+8] ;R72 mov [bp+2],ax mov ax,[bp+4] ;R72 ;R118 xchg ax,[bp+10] ;R72 xchg ax,[bp+6] ;R118 mov [bp+4],ax ;R72 xchg bp,sp popf ;R72 pop ax FAR_JMP ,0e000h ;R39 end STAT8042 EQU 64H ;R141 PUBLIC EXCEPTION_HDLR PUBLIC KILL_MACHINE EXCEPTION_HDLR: KILL_MACHINE: MOV AL,0FEH OUT STAT8042,AL SHUT_HLT: CLI HLT JMP SHORT SHUT_HLT ;R46 - start ;R47 ifndef SMBASE_USE_E000H ALIGN 4 Public GDTR1 GDTR1: ; global descriptor table register ;R56 dw 8*3 ; LIMIT ;R95 dw 8*4 ;R56; LIMIT ;R145 ifndef Flash_16K_8K_8K_Unit dw 8*5 ;R95; LIMIT else dw 8*6 ;R145 LIMIT endif ;Flash_16K_8K_8K_Unit ;R145 dw offset GDT1 dw 0fh ; in 0F000h segment Public GDT1 GDT1: ; null descriptor dw 0 ; limit dw 0 ; base db 0 ; hibase db 0 ; access db 0 ; hilimit db 0 ; msbase Public CODE1_DT CODE1_DT: ; cs - prom code segment CODE1_INDEX = ((offset CODE1_DT - offset GDT1)/8) SHL 3 dw 0ffffh ; limit dw 0 ; base a15-a0 db 0fh ; hibase a23-a16, assume we have 64k prom db 9fh ; access db 0 ; hilimit db 0 ; msbase a31-a24 Public DATA1_DT Public DATA1_INDEX DATA1_DT: ; ds - first 64k segment DATA1_INDEX = ((OFFSET DATA1_DT - OFFSET GDT1)/8) SHL 3 dw 0ffffh ; limit dw 0 ; base data segment points to db 0 ; hibase ; 00000000 db 93h ; access db 08fh ; hilimit (4GB) db 0 ; msbase ;R47 endif ;SMBASE_USE_E000H ;R46 - end ;R56 - start ifdef PNP_BIOS ;R145-start ifdef Flash_16K_8K_8K_Unit public F000_DT public F000_index F000_DT: ; ESCD F000_index = ((OFFSET F000_DT - OFFSET GDT1)/8) SHL 3 dw 0ffffh ; limit dw (F000_BASE AND 0FFFFh) ; base address db ((F000_BASE SHR 16) AND 0FFh) ; hibase db 93h ; access db 0 ; hilimit db ((F000_base SHR 24) AND 0FFh) ; msbase endif ;Flash_16K_8K_8K_Unit ;R145-end ifdef FLASH_SUPPORT ;R153 public ESCD_DT public ESCD_INDEX ;R56A ifndef ESCD_BASE ;R100 ESCD_BASE EQU 0FFFF8000h ;R56A endif ;ESCD_BASE ESCD_DT: ; ESCD ESCD_INDEX = ((OFFSET ESCD_DT - OFFSET GDT1)/8) SHL 3 dw 0ffffh ; limit dw (ESCD_BASE AND 0FFFFh) ; base address db ((ESCD_BASE SHR 16) AND 0FFh) ; hibase db 93h ; access db 0 ; hilimit db ((ESCD_BASE SHR 24) AND 0FFh) ; msbase ;R56 - end endif ;FLASH_SUPPORT ;R153 ;R95 - start public F0DATA_DT public F0DATA_INDEX F0DATA_DT: ; F000 data F0DATA_INDEX = ((offset F0DATA_DT - offset GDT1)/8) SHL 3 dw 0ffffh ; limit dw 0 ; base address db 0fh ; hibase db 93h ; access db 0 ; hilimit db 0 ; msbase endif; PNP_BIOS ;R95 - end ;R23;[]==============================================================[] ;R23; ;R23; REDO: ;R23; ;R23; This routine is called by the reset vector at F000:E05B ;R23; after a power-up. It determines whether this is a virtual ;R23; shutdown or a normal boot. If it is a normal boot, we ;R23; juggle a few cache's and then go on to POST. ;R23; ;R23;Saves: NONE ;R23; ;R23;Entry: NONE ;R23;Exit: NONE ;R23; ;R23;Author: Award ;R23;Date: 04/18/90 ;R23; ;R23; Name | Date | Description ;R23; --------------------------------------------------------------- ;R23; TIM | 18-Apr-90 | Update to 4.0 ;R23; ;R23;[]==============================================================[] ;R23 ;R23 PUBLIC REDO ;R23REDO PROC NEAR ;R23 ;R23 ror edx,16 ; high dx = cpu type ;R23; ;R23; Test if this was a virtual shutdown. ;R23; ;R23 ;R23 cli ;R23 cld ;R23 in al,STAT8042 ; was this a user or prog reset ? ;R23 test al,4 ;R23 jnz short redo1 ; virtual shutdown... ;R23 ;R23 mov ax,cs ;R12 ;R23 mov ss,ax ; ss = cs ;R12 ;R23 ;R23;R02 start ;R23ifdef PM_SUPPORT ;R23 call CT_Sleep_Detect ;R23 jnz short redo1 ; virtual shutdown... ;R23endif ;PM_SUPPORT ;R23;R02 end ;R23 xor al,al ; al = early detect ;R12 ;R23 ror edx,16 ; dx = CPU ID ;R12 ;R23 call CPU_Detect ;R12 ;R23;R11 call CPU_Init ;R12 ;R23 jmp Pup_Wait ; first time power up ;R23REDO ENDP ;R23 ;R23 ;R23;[]==============================================================[] ;R23; ;R23; REDO1: ;R23; ;R23; ;R23; Handle the virtual shutdown. The shutdown code is in byte 0Fh ;R23;of CMOS. The following codes can be found can be used: ;R23; ;R23; ;R23;00h = Power on or soft reset ;R23;01h = Memory sizing pass ;R23;02h = Memory test pass ;R23;03h = Memory test fail ;R23;04h = POST end; boot system ;R23;05h = Flush keyboard buffer, do an EOI, jmp to dword 40:67 ;R23;06h = Protected mode test pass ;R23;07h = Protected mode test fail ;R23;08h = Memory sizing fail ;R23;09h = INT 15h block move return ;R23;0Ah = jmp to dword 40:67 ;R23; ;R23;Saves: NONE ;R23; ;R23;Entry: NONE ;R23;Exit: NONE ;R23; ;R23;Author: Award ;R23;Date: 04/18/90 ;R23; ;R23; Name | Date | Description ;R23; --------------------------------------------------------------- ;R23; TIM | 18-Apr-90 | Update to 4.0 ;R23; ;R23;[]==============================================================[] ;R23 ;R23REDO1 PROC NEAR ;R23 ;R23;R02 start ;R23ifdef PM_SUPPORT ;R23; NOTE: To resume from the SUSPEND mode on a 386SL system, accessing ;R23; BIOS stack is not allowed before handling the RESUME process. ;R23 ;R23 mov al,0fh NMI_OFF ; check cmos shutdown type ;R23 out CMOS,al ;R23 newiodelay ;R23 in al,CMOS+1 ;R23 newiodelay ;R23 cmp al,RESUME_SHUTDOWN_BYTE ; user return sleep mode ;R23 jne redo1_0 ;R23 jmp CT_RESUME_HANDLE ;R23redo1_0: ;R23endif ;PM_SUPPORT ;R23;R02 end ;R23 ;R23;R07 start ;R23ifdef PM_SUPPORT ;R23 mov ax,G_RAM ;R15 ;R23 mov es,ax ;R15 ;R23 cmp es:USER_REBOOT,CTRL_ALT_DEL ;R15 ;R23 je short Not_SMI_Start ;R15 ;R23 jmp Ct_Check_SMI_Start ;See if it is a SMI request ;R23 ;issue(AMD & U5 CPU) ;R23 Public Not_SMI_Start ;R23Not_SMI_Start: ;R23endif ;PM_SUPPORT ;R23;R07 end ;R23 ;R23 mov ax,BIOS_STK ; setup stack ;R23 mov ss,ax ;R23 mov sp,offset BIOSSTK_TOP ;R23 ;R23;R05 - start ;R23 mov al,8fh ; cmos shutdown byte ;R23 out CMOS,al ;R23 newiodelay ;R23 in al,CMOS+1 ;R23 ;R23 push ax ;R23 or al,al ;R23 jz short Not_ShutDown ;R23;R05 - end ;R23 ;R23 call Init_Cyrix_Reg ;R21 ;R23 ;R23 mov al,1 ;R06 ;R23 call Restore_Cyrix_Reg ;R06 ;R23 ;R23 call Ct_Restore_Cyrix_Reg ;R14A ;R23 ;R23;R14 - starts ;R23;R14B mov ax,0C3C3h ;lock Cyrix registers ;R23;R14B out 22h,al ;R23;R14B in al,23h ;R23;R14B or al,1 ;R23;R14B xchg ah,al ;R23;R14B out 22h,al ;R23;R14B xchg ah,al ;R23;R14B out 23h,al ;R23;R14 - ends ;R23 ;R23 call Cpu_Init ;R23;R20 - start ;R23ifdef MP_SUPPORT ;R23 extrn Cpu_Apic_Init:near ;R23 call Cpu_Apic_Init ;R23endif; MP_SUPPORT ;R23;R20 - end ;R23 ;R23 mov si,offset IntCache_Item ;R23 call GetItem_Cmos ;R23 or al,al ;R23 jz short Not_Enable_486_Cache ;R23 ;R23; mov al,CMOS_AWARD_CACHE NMI_OFF ;R23; call Get_Cmos ;R23; test al,SECONDARY_CACHE ;R23; jz short Not_Enable_486_Cache ;R23 ;R23 mov al,1 ; al = cache on ;R12 ;R23 call CPU_Cache ;R12 ;R23Not_Enable_486_Cache: ;R22 ;R23 ;R23;R05 mov al,8fh ; cmos shutdown byte ;R23;R05 out CMOS,al ;R23;R05 newiodelay ;R23;R05 in al,CMOS+1 ;R23Not_ShutDown: ;R05 ;R23 pop ax ;R05 ;R23; begin -workaround 386SL ;R23; This delay loop is here to fix QAPLUS extended memory test for 386SL ;R23; This loop should be taken away once bug is solved in hardware ;R23; ;R23;Deleted IFDEF DELAY_FOR_SHUTDOWN_BYTE_READ ;R23;Deleted mov cx,100 ;R23;Deleted loop $ ;R23;Deleted ENDIF ;R23 ;R23 mov ah,al ;R23 cmp al,9 ; if 9 or 0ah don't re-init 8259s ;R23 jae short shut_branch ;R23 ;R23; ;R23; reset 8259s after virtual shut down ;R23; ;R23 ;R23int8259init: ;R23 xor al,al ;R23 out MATH_PORT+1,al ; reset the co-processor ;R23 mov bx,ax ; save the shutdown code ;R23 ;R23 mov ax,cs ;R23 mov ds,ax ;R23 ;R23 mov si,offset int_inits ;R23 mov cx,size_int_inits ;R23 ;R23int8259_lp1: ;R23 lodsw ; get the port ;R23 mov dx,ax ; put in correct reg ;R23 lodsb ; get byte to ouput ;R23 out dx,al ;R23 loop short int8259_lp1 ;R23 ;R23 mov ax,bx ; restore shutdown ;R23 ;R23; ;R23; reset shutdown byte ;R23; ;R23 ;R23shut_branch: ;R23 mov al,8fh ; NMI off ;R23 out CMOS,al ;R23 newiodelay ;R23 xor al,al ;R23 out CMOS+1,al ;R23 ;R23 ;check other shut down modes ;R23 ;R23 cmp ah,9 ;R23 jne short Chk_2 ;R23 jmp Exc9hdlr ;R23 ;R23chk_2: ;R23 cmp ah,5 ;R23 je short jmp_5init ; user return from virtual mode ;R23 ;R23 cmp ah,0ah ; user return from virtual mode without 8259 init ;R23 je short jmp_ioinit ;R23 ;R23;R02 start ;R23ifdef PM_SUPPORT ;R23 cmp ah,RESUME_SHUTDOWN_BYTE ; user return sleep mode ;R23;R09 je short jmp_RESUME_HANDLE ;R23 je jmp_RESUME_HANDLE ;R09 ;R23endif ;PM_SUPPORT ;R23;R02 end ;R23 ;R23 cmp ah,4 ; user return from virtual w/ boot request ;R23 jne short chk_2a ;R23 ;R23; ;R23; enable parity, nmi (mode 4) ;R23; ;R23 ;R23 call Enable_Parity ; additional code clear parity ;R23 ;R23; ;R23; enabling nmi is a bug fix which must stay in place here... ;R23; ;R23 ;R23 mov al,0fh NMI_ON ; enable nmi ;R23 call Get_Cmos ;R23 ;R23 int 19h ; boot ;R23 ;R23chk_2a: ;R23 xor bp,bp ; memory test fail ;R23;R23 - start ;R23 call A20_On ; turn on A20 to match ;R23 ; cold boot status ;R23;R23 - end ;R23;R01 - start ;R23; ;R23; Restore CPU type from G_RAM:CPU_TYPE_FLAG for warm boot ;R23; ;R23 mov al,0eh ;R03 ;R23 call get_cmos ;R03 ;R23 test al,CKSM_STATUS+RTC_STATUS ;R03 ;R23 jz short @F ;R03 ;R23 ;R23 mov ax,G_RAM ;R23 mov ds,ax ;R23 assume ds:G_RAM ;R23 mov al,CMOS_AWARD_2 NMI_OFF ;R23 mov ah,ds:CPU_TYPE_FLAG ;R23 call Set_Cmos ;R23 ;R23 mov al,CMOS_OVERRIDE NMI_OFF ;R04 ;R23 call get_cmos ;R04 ;R23 and al,00111111b ;R04 ;R23 mov ah,ds:CPU_CLOCK ;R04 ;R23 and ah,00000011b ;R04 ;R23 shl ah,6 ;R04 ;R23 or ah,al ;R04 ;R23 mov al,CMOS_OVERRIDE NMI_OFF ;R04 ;R23 call Set_Cmos ;R04 ;R23 ;R23@@: ;R03 ;R23;R09 - start ;R23 mov al,CMOS_AWARD_2 NMI_OFF ;R23 call Get_Cmos ;R23 and al,CPU_TYPE_MASK ;R23 cmp al,TYPE_TI486SXL2 ;R23 jne short @F ;R23 ;R23 mov dx,CPU_TI486SXL ;R23 mov ah,dl ;R23 mov al,CMOS_AWARD_2 NMI_OFF ;R23 Call Set_Cmos ;R23 ;R23 mov al,OVERRIDE NMI_OFF ;R23 Call Get_Cmos ;R23 and al,Not Clock_Mode ;R23 mov ah,dh ;R23 or ah,al ;R23 mov al,OVERRIDE NMI_OFF ;R23 Call Set_Cmos ;R23@@: ;R23;R09 - end ;R23;R01 - end ;R23 jmp Pup_Wait ;R23 ;R23; ;R23; clear keyboard buffer and do an end-of-interrupt (mode 5) ;R23; ;R23 ;R23jmp_5init: ;R23 in al,DATA8042 ; clear keyboard ;R23 mov al,END_OF_INT ; clear interrupts ;R23 NEWIODELAY ;R23 out A8259,al ;R23 ;R23; ;R23; jmp dword 40:[67] (mode 5 & 10) ;R23; ;R23 ;R23jmp_ioinit: ; jmp to dword at 40:67 ;R23 ;R23 mov eax,cr0 ;R23 or al,10h ; enable ET bit ;R23 mov cr0,eax ;R23 ;R23 mov ax,G_RAM ;R23 mov ds,ax ;R23 jmp ds:dword ptr ROM_MODULE_OFFSET ;R23 ;R23;R02 start ;R23ifdef PM_SUPPORT ;R23jmp_RESUME_HANDLE: ;R23 mov ax,cs ;R23 mov ss,ax ;R23 call CT_RESUME_HANDLE ;R23endif ;PM_SUPPORT ;R23;R02 end ;R23 ;R23REDO1 ENDP ;**************************************** ;* * ;* MANUFACTURING POST DEFAULTS * ;* * ;**************************************** ;R18 MAN_DEFAULT_TBL DB 0,0,0,0,0,0,0,0,0,0 ;R80;[]==============================================================[] ;R80; ;R80;SETUP_STACK: ;R80; ;R80; Reserve stack space for user-interface routines, CMOS, etc. ;R80; ;R80; ;R80;Saves: AX,CX ;R80; ;R80;Entry: NONE ;R80;Exit: NONE ;R80; ;R80;Notes: 1. TOTALSTACK is defined in STACK.EQU. ;R80; ;R80;Author: Tim Lewis ;R80;Date: 04/18/90 ;R80; ;R80; Name | Date | Description ;R80; --------------------------------------------------------------- ;R80; TIM | 18-Apr-90 | Initial revision ;R80; ;R80;[]==============================================================[] ;R80 align 4 ;R25 ;R80 PUBLIC SETUP_STACK ;R80SETUP_STACK PROC NEAR ;R80 ;R80 ;R80; Begin save BP ;R80 pop bx ; pop return address ;R80 ;R80 sub sp,DATAAREASIZE ; reserve stack size for setup ;R80 ;R80 mov bp,sp ;R80 ;R80; Begin save BP ;R80 push ds ; save BP in G_RAM:Temp_BP ;R80 push ax ;R80 mov ax, G_RAM ;R80 mov ds,ax ;R80 ASSUME DS:G_RAM ;R80 mov word ptr [Temp_BP], bp ;R80 ASSUME DS:DGROUP ;R80 pop ax ;R80 pop ds ;R80 ;R80 push bx ; put return address back ;R80; End save BP ;R80 ;R80 ret ;R80SETUP_STACK ENDP ;R80 align 4 ;R25 public Do_F000_Shadow Do_F000_Shadow PROC Near ;R90 - start extrn F000_Shadow_W:near ;R90A extrn F000_Shadow_R:near ;R90A push si call F000_Shadow_W ;enable F000 shadow R/W mov ax,cs mov ds,ax mov es,ax pop si call si call F000_Shadow_R ;enable F000 shadow readonly ;R90 - end ;R90 push si ;R90 ;R90;Move codes from ROM to temporary area ;R90 mov si,0f000h ;source area ;R90 extrn TEMP_MEM:ABS ;R90 mov di,TEMP_MEM ;destination area ;R90 mov cx,8000h ;64k ;R90 extrn Move_Codes:Near ;R90 call Move_Codes ;R90 ;R90 pop si ;R26A push si ;R26 ;R90 call si ;R26 start ;R26A pop si ;R26A cmp si,offset SHADOW_DR ;R26A jne short @F ;R26A mov ax,g_ram ;R26A mov ds,ax ;R26A assume ds:g_ram ;R26A test byte ptr ds:POST_FLAG,DRIVE1_ABSENT ;R26A jnz short Drive1_is_absent ;R26A test byte ptr FIXED_TYPE[bp],0fh ;R26A jnz short @F ;R26ADrive1_is_absent: ;R26A push es ;R26A pop ds ;R26A lea si,DGROUP:DRV0 ;move DRV0 parameter to DRV1 ;R26A lea di,DGROUP:DRV1 ;R26A mov cx,16 ;R26A rep movsb ;R26A lea di,DGROUP:DRV0 ;clear DRV0 parameter ;R26A xor ax,ax ;R26A mov cx,8 ;R26A rep stosw ;R26A@@: ;R26 end ;R90 ;R90;Jump to temporay area to execute shadowing ;R90 FAR_JMP ,TEMP_MEM ;R90From_RAM_To_ROM: ;R90 cli ;disable interrupt before f000 shadow disable ;R90 ;R90 extrn F000_Shadow_W:Near ;R90 call F000_Shadow_W ;enable F000 shadow writeable ;R90 mov si,TEMP_MEM ;source area ;R90 mov di,0f000h ;destination area ;R90 mov cx,8000h ;64k ;R90 call Move_Codes ;R90 extrn F000_Shadow_R:Near ;R90 call F000_Shadow_R ;enable F000 shadow readonly ;R90 ;R90 sti ;enable interrupt after f000 shadow enable ;R90 ;R90 FAR_JMP ,0F000H ;R90Return_From_RAM: ret Do_F000_Shadow ENDP ;[]==============================================================[] ; ;PUP_WAIT: ; ; Disable the cache and then fall into POST ; ;Saves: NONE ; ;Entry: BP POST code to display ; ;Exit: NEVER ; ;Author: Award ;Date: 04/18/90 ; ; Name | Date | Description ; --------------------------------------------------------------- ; TIM | 23-Aug-90 | Now only do 486 cache turn off here. ; TIM | 18-Apr-90 | Update to 4.0 ; ;[]==============================================================[] align 4 ;R25 PUBLIC PUP_WAIT PUP_WAIT PROC NEAR mov ax,cs mov ss,ax ; ss = cs ;Deleted ;R14 - start ;Deleted ifdef WAIT_CHIPSET_TO_COME_UP ;Deleted xor cx,cx ;Deleted loop $ ;Deleted endif; WAIT_CHIPSET_TO_COME_UP ;Deleted ;R14 - end ;Begin 486 only cache off ; ; Disable the 486 internal cache. ; ;Program chipset registers before POST POST_CODE 0c0h mov sp,0F80Bh extrn Ct_Very_Early_Init:Near jmp Ct_Very_Early_Init ;R80 public PUP_WAIT1 ;R80PUP_WAIT1: ;R80 extrn Power_On_Delay:word ;R80 mov cx,cs:[Power_On_Delay] ;R80 jcxz short @F ;R80Wait_Chipset: ;R80 NEWIODELAY ;R80 loop short Wait_Chipset ;R80@@: ;R80 mov ax,BIOS_STK ;R80 mov ss,ax ;R80 mov sp,offset POSTSTK_TOP ;R80 ;R80 call Setup_Stack ;R80 PUP_WAIT ENDP ;R80 ;R80;[]==============================================================[] ;R80; ;R80; POST_1s: ;R80; ;R80; Test processor status flags. If bad, halt system. ;R80; ;R80;Saves: NONE + NO STACK ;R80; ;R80;Entry: NONE ;R80;Exit: NONE ;R80; ;R80;Author: Award ;R80;Date: 04/18/90 ;R80; ;R80; Name | Date | Description ;R80; --------------------------------------------------------------- ;R80; TIM | 18-Apr-90 | Update to 4.0 ;R80; ;R80;[]==============================================================[] ;R80 ;R80 PUBLIC POST_1S ;R80POST_1S PROC NEAR ;R80 ;R80; prevent hang on post 4 ;R80 ;R18 POST_CODE 1 ;R18 stc ; check carry ;R18 jnc short post_1_fail ;R18 clc ;R18 jc short post_1_fail ;R18 ;R18 xor ax,ax ; check zero clear ;R18 jnz short post_1_fail ;R18 jo short post_1_fail ; overflow clear ;R18 js short post_1_fail ; sign clear ;R18 ;R18 or ax,-1 ;R18 jz short post_1_fail ; not zero set ;R18 jns short post_1_fail ; sign set ;R18 ;R18 mov ax,7fffh ;R18 add ax,7fffh ; overflow set ;R18 jno short post_1_fail ;R18 ;R18 jmp short Post_2s ;R18 post_1_fail: ;R18 jmp haltsystem ;R80POST_1S ENDP ;R80 ;R80;[]==============================================================[] ;R80; ;R80; POST_2S: ;R80; ;R80; Test processor registers. If bad, halt system. Test all ;R80; registers except CS with patterns 0ffffh, 0000h, 5555h ;R80; and 0aaaah. ;R80; ;R80;Saves: NONE + NO STACK ;R80; ;R80;Entry: NONE ;R80;Exit: NONE ;R80; ;R80;Author: Award ;R80;Date: 04/18/90 ;R80; ;R80; Name | Date | Description ;R80; --------------------------------------------------------------- ;R80; TIM | 18-Apr-90 | Update to 4.0, add 386/486 register tests. ;R80; ;R80;[]==============================================================[] ;R80 ;R80 PUBLIC POST_2S ;R80POST_2S PROC NEAR ;R80 ;R80 ;R18 POST_CODE 2 ;R18 ;R18 mov eax,-1 ; set all registers to -1 ;R18 post_2s1: ;R18 mov ebx,eax ;R18 mov ecx,ebx ;R18 mov edx,ecx ;R18 mov esi,edx ;R18 mov edi,esi ;R18 ;R18 mov es,di ;R18 mov ds,si ;R18 mov fs,dx ;R18 mov gs,cx ;R18 mov bp,bx ;R18 mov sp,ax ;R18 ;R18 cmp ebx,eax ; check a 32-bit register ;R18 jne short post_2s_fail ;R18 ;R18 cmp sp,ax ; check a stack register ;R18 jne short post_2s_fail ;R18 ;R18 or eax,eax ; finished? ;R18 jz short post_2s_cont ; yes... ;R18 ;R18 inc eax ; set registers to all 0's ;R18 jmp post_2s1 ; do it over... ;R18 ;R18 post_2s_fail: ;R18 jmp HaltSystem ;R18 ;R18 post_2s_cont: ;R18 mov eax,55555555h ;R18 post_2s_cont1: ;R18 mov ebx,eax ;R18 mov ecx,ebx ;R18 mov edx,ecx ;R18 mov esi,edx ;R18 mov edi,esi ;R18 ;R18 mov es,di ;R18 mov ds,si ;R18 mov fs,dx ;R18 mov gs,cx ;R18 mov bp,bx ;R18 mov sp,ax ;R18 ;R18 cmp ebx,eax ; check a 32-bit register ;R18 jne short post_2s_fail ;R18 ;R18 cmp sp,ax ; check a stack register ;R18 jne short post_2s_fail ;R18 ;R18 cmp eax,55555555h ;R18 jne short post_2s_cont2 ;R18 ;R18 mov eax,0aaaaaaaah ;R18 jmp short post_2s_cont1 ;R18 ;R18 post_2s_cont2: ;R80;R61 start ;R80 call E000_64K_shadow_RW ;R80 mov si,5000h ;R80 mov di,0e000h ;R80 mov cx,8000h ;R80 call Move_Codes ;R80 call E000_64K_shadow_R ;R80;R61 end ;R80 FAR_JMP ,0E000H ;R80POST_2S ENDP PAGE ;R77;R44 start ;R77 public Preint_19 ;R77Preint_19: ;R77 ;R77ifdef AVIDEO_AT_F000 ;R55 ;R77 extrn Disable_E000_ROM_Shadow:near ;R55 ;R77 call Disable_E000_ROM_Shadow ;R55 ;R77 ;R77ifdef SCAN_E000_ISA_ROM ;R75 ;R77 mov bx,0e000h ;R75 ;R77 mov dx,0e080h ;R75 ;R77 call R_MOD_CK ;R75 ;R77endif; SCAN_E000_ISA_ROM ;R75 ;R77 ;R77else; AVIDEO_AT_F000 ;R55 ;R77 ;R77 call E000_64K_shadow_RW ;R77 mov ax,0e000h ;R77 mov es,ax ;R77 xor di,di ;R77;R50A ifdef PNP_BIOS ;R50 ;R77;R50A mov cx,0f000h/2 ;R77;R50A else ;PNP_BIOS ;R50 ;R77;R50A mov cx,8000h ;R50 ;R77;R50A endif ;PNP_BIOS ;R50 ;R77;R50A start ;R77;R55 ifdef AVIDEO_AT_F000 ;R77;R55 mov cx,8000h ;R77;R55 else ;AVIDEO_AT_F000 ;R77 mov cx,0f000h/2 ;R77;R55 endif ;AVIDEO_AT_F000 ;R77;R50A end ;R77 mov ax,0ffffh ;R77 cld ;R77 rep stosw ;R77 call E000_64K_shadow_R ;R77 ;R77endif; AVIDEO_AT_F000 ;R55 ;R77;R44 end ;R77 - starts public Preint_19 Preint_19: ;r119 start ifdef RPB_ENABLED ; RXX ;M01 Post_Func_Call rpb_is_running ; check if interface enabled ;M01 jc clear_E000 call rpb_f000_is_running ;M01 jc clear_E000 ;M01 Post_Func_Call rpb_set_dos_mode jmp call_int19 clear_E000: endif ; RPB_ENABLED ;r119 end CLEAR_E000_METHOD EQU ((POST_ORG_E8 SHL 4) + RELEASE_E000_FOR_PCI) IF CLEAR_E000_METHOD EQ 00h ifdef AVIDEO_AT_F000 call Disable_E000_ROM_Shadow ;prg the chipset to ;direct of E000 access to ISA mov bx, 0e000h mov dx, 0e080h call R_MOD_CK else ;AVIDEO_AT_F000 SHOULD_CLEAR_E000 EQU 1 mov ax, 0E000h mov cx, 0F000h/2 call Clear_E000_Shadow_For_UMB endif ;AVIDEO_AT_F000 ENDIF ;CLEAR_E000_METHOD EQ 00h IF CLEAR_E000_METHOD EQ 10h SHOULD_CLEAR_E000 EQU 1 ifdef AVIDEO_AT_F000 mov cx, 08000h/2 else ;AVIDEO_AT_F000 mov cx, 07000h/2 endif ;AVIDEO_AT_F000 mov ax, 0E800h call Clear_E000_Shadow_For_UMB ENDIF ;CLEAR_E000_METHOD EQ 10h IF CLEAR_E000_METHOD EQ 11h SHOULD_CLEAR_E000 EQU 1 ;------------------------------------------------------------------------ ; In PCIPOST.ASM, we release the E0000-E7FFF shadow RAM for PCI ROM. ; ; If this area is assigned for PCI ROM, the E shadow cannot be disabled ; any more. ; ; Also, we have to clear the shadow RAM according to the shadow RAM used in ; order that the EMM386 can use this area as UMB. In PCIPOST.ASM, it can only ; clear the RAM before E8000h. Therefore, we just have to kill code from ; E8000 onward ! ;------------------------------------------------------------------------- ifdef AVIDEO_AT_F000 mov cx, 08000h/2 mov ax, 0E800h ifdef PCI_BUS ;R77A push 0E000h pop ds mov si, offset E000_USED_BY_PCI ;check if E000 shadow RAM mov bl, ds:[si] ; occupied by PCI ROM or bl, bl ;occupied ? jnz short Clear_E000_Shadow ;yes, go kill shadow RAM ;from E8000-EFFFF endif; PCI_BUS ;R77A call Disable_E000_ROM_Shadow ;else, prg the chipset to ;direct of E000 access to ISA mov bx, 0e000h mov dx, 0e080h call R_MOD_CK jmp short End_Clear_E800_Shadow else ;AVIDEO_AT_F000 mov cx, 07000h/2 mov ax, 0E800h endif ;AVIDEO_AT_F000 Clear_E000_Shadow: call Clear_E000_Shadow_For_UMB End_Clear_E800_Shadow: ENDIF ;CLEAR_E000_METHOD EQ 11h ;r119 start ifdef RPB_ENABLED ; RXX call_int19: endif ; RPB_ENABLED ;r119 end POST_CODE 0ffh ;R131 - starts ifdef VSA_VGA extrn Gx86_VSA_Final_Init:near call Gx86_VSA_Final_Init endif ;VSA_VGA ;R131 - ends ;R151 - starts ifdef Special_Before_INT19 extrn Ct_Before_INT19:near call Ct_Before_INT19 endif ;Special_Before_INT19 ;R151 - ends ;R113A ;R113 start ;R113A ifdef Gx86_PCI_REG ;R113A mov al, 0C3h ;R113A out 22h, al ;R113A mov al, 0E0h ;R113A out 23h, al ;R113A mov al, 0C2h ;R113A out 22h, al ;R113A mov al, 0C2h ;R113A out 23h, al ;R113A ;R113A mov dx, 0cf8h ;R113A mov eax, 800090d0h ; Index to GX5510 ;R113A out dx, eax ;R113A ;R113A mov dx, 0cfch ;R113A mov ax, 5000h ; Tell VSA to finish initialization ;R113A out dx, ax ;R113A endif ;Gx86_PCI_REG ;R113A ;R113 end ;R141 start ifdef Trend_AntiVirus mov ax,4000h mov ds,ax cmp dword ptr ds:[0],'CHWY' ;check have virus ROM jne short Not_trend ;no skip virus ROM initial push ds call Open_PM_RAM ;open F000 shadow writeable pop ds push 0f000h pop es ;point ES to 0F000h xor si,si mov cx,ds:[si+4] ;get virus ROM size cld mov di,AntiVirus_Offset rep movsw ;move Virus code to F000 shadow from 4000h:0 ;decompress in POST 99s of E8POST.ASM) db 9ah ;far call 0f000h:AntiVirus_Offset ;R141A dw 6 ;skip ChapAwayVirus size record and signature dw 10h ;R141A dw 0f000h+(AntiVirus_Offset shr 4) Not_trend: ;----- clear 4000h:0 area data mov ax,4000h mov es,ax mov cx,8000h ;64k word xor ax,ax rep stosw ;clear temp area for virus ;----- endif ;Trend_AntiVirus ;R141 end ;R125C - start ;Enable boot from LAN first ifdef HOTKEY_TO_BOOT_LAN LAN_BOOT_SUPPORT EQU 1 endif; HOTKEY_TO_BOOT_LAN ;R125C - end ;R125B - start ifdef LAN_BOOT_SUPPORT mov ax,G_RAM mov ds,ax assume ds:G_RAM ;Boot from INT 18H first if user enable in CMOS setup test byte ptr ds:SYSTEM_FLAG,BOOT_LAN ;boot LAN ? ;R162 jz short NoInt18Hooked jz short NotLANFirst ;R162 ;check if INT 18H hooked by other ROMs cmp word ptr ds:[Int18],offset cs:Int18_Hdlr jne short YesTryInt18 mov ax,cs ;INT 18 hooked ? cmp word ptr ds:[Int18+2],ax je short NoInt18Hooked ;no, YesTryInt18: int 18H ;boot to LAN NoInt18Hooked: ;R162 - start call BootFromBEVs ;try boot from BEVs NotLANFirst: ;R162 - end endif; LAN_BOOT_SUPPORT ;R125B - end xor dx,dx ;R144 and esp,0000ffffh ;R161 int 19h ifdef SHOULD_CLEAR_E000 ;------------------------------------------------- ;Input : AX = starting addr. to be cleared ; CX = no. of words to be cleared ;------------------------------------------------- Clear_E000_Shadow_For_UMB Proc Near pusha call E000_64K_shadow_RW popa mov es, ax xor di, di mov ax, -1 cld rep stosw call E000_64K_shadow_R ret Clear_E000_Shadow_For_UMB Endp endif ;SHOULD_CLEAR_E000 ;R77 - ends ;R130 - start ifdef Trend_AntiVirus ;R141 public Virus_Used_Shadow ;R141Virus_Used_Shadow label near ;R141 dw 0 align 16 db '$CHWY' Set_Shadow_WrProt proc far call Close_PM_RAM ;R141 ;R163 start xor bx,bx mov cx,1000h extrn WAIT_REFRESH:near call WAIT_REFRESH ;R163 end ;R141 pushad ;R141 push es ;R141 push 0f000h ;R141 pop es ;R141 mov ax, word ptr es:[Virus_Used_Shadow] ;R141 mov dh, al ;R141;R137 - statr ;R141 call Ct_Shadow_Unit ;R141 mov bl, 4 ;R141 cmp cx, 4000h ;R141 je short @F ;R141 mov bl, 8 ;R141@@: ;R141;R137 - end ;R141 pushad ;R141 call Ct_Shadow_R ;Shadow protect write ;R141 popad ;R141 cmp dh, ah ;R141 jz short @f ;R141;R137 add dh, 4 ;R141 add dh, bl ;R137 ;R141 jmp short @B ;R141@@: ;R141 pop es ;R141 popad retf Set_Shadow_WrProt endp endif; Trend_AntiVirus ;R130 - end ;R99 - start PUBLIC BAD_DISK_MSG BAD_DISK_MSG: ifdef Special_Bad_Disk_Message db Special_Bad_Disk_Message else ;Special_Bad_Disk_Message DB 'DISK BOOT FAILURE, INSERT SYSTEM DISK AND PRESS ENTER',CR,LF,00h endif ;Special_Bad_Disk_Message ;R99 - end ;[]==============================================================[] ; ;INT_19S: ; ; Read O/S boot block in at 0000:7C00h and jumps to it. ; ; ;Saves: NONE ; ;Entry: NONE ;Exit: NONE ; ;Author: Award ;Date: 04/18/90 ; ; Name | Date | Description ; --------------------------------------------------------------- ; TIM | 18-Apr-90 | Initial revision ; ;[]==============================================================[] ;R136A start Display_str: push ax push cx mov ah,3 xor bh,bh int 10h pop cx mov ax,1301h mov bx,7 int 10h pop ax ret ;R136A end ;R28 start ifdef CD_ROM Xlat_CDsec_CHS: shl eax,2 ;CDsec*4 inc eax mov edx,eax shr edx,16 ;R123C mov cx,63*16 mov cx,63*255 ;R123C div cx xchg ax,dx ;DX = Cylinders mov cl,63 div cl ;AL = Heads & AH = Sectors mov cl,ah and cl,3fh mov ch,dl shl dh,6 or cl,dh mov dh,al ret ;R43 start CD_ROM_TEMP_SEG EQU 2000h CD_ROM_TEMP_OFF EQU 800h TEMP_OFF EQU 700h Option_Str db 0dh,'Enter a choice : 1',8 Option_Str_len equ $ - offset Option_Str Floppy_Str db '1.2MB ' db '1.44MB ' db '2.88MB ' ;R43 end C_DRIVE EQU 81h ;R37 start public Model_Number_Len ;R52 Model_Number_Len equ 40 ifndef NO_CDROM_BOOT_MESSAGE ;R78 CD_Boot_Str0 db 'Boot from ATAPI CD-ROM : ' CD_Boot_Str0_len equ $ - offset CD_Boot_Str0 endif ;NO_CDROM_BOOT_MESSAGE ;R78 CD_Boot_Str2 db ' Failure ...' ;R53 CD_Boot_Str1 db 0dh,0ah CD_Boot_Str1_len equ $ - offset CD_Boot_Str1 CD_Boot_Str2_len equ $ - offset CD_Boot_Str2 ;R53 Special_CDROM_Drive db 'GCD-R520B' ;R52A Special_CDROM_Len0 equ $ - offset Special_CDROM_Drive ;R52A ;R37 end else ;CD_ROM C_DRIVE EQU 80h endif ;CD_ROM A_DRIVE EQU 0 CD_DRIVE EQU 80h None_Drive EQU 0ffh ;R66 SCSI_Drive EQU 0feh ;R88 LS120_DRIVE EQU 7fh ;R115 Boot_Seq_Drive: ;R66 DB A_DRIVE, C_DRIVE, CD_DRIVE ;R66 DB C_DRIVE, A_DRIVE, CD_DRIVE ;R88 start ifdef HDD_Boot_Selectable DB A_DRIVE, C_DRIVE, SCSI_DRIVE ;R93 start ;R93A start ;ifdef support_only_C_boot ; DB C_DRIVE, None_DRIVE, None_DRIVE ;else ;support_only_C_boot ;R93A end ;R93 end DB C_DRIVE, A_DRIVE, SCSI_DRIVE ;R93A endif ;support_only_C_boot ;R93 else ;HDD_Boot_Selectable ;R88 end DB A_DRIVE, C_DRIVE, None_DRIVE ;R66 ;R93 start ;R93A start ;ifdef support_only_C_boot ; DB C_DRIVE, None_DRIVE, None_DRIVE ;else ;support_only_C_boot ;R93A end ;R93 end DB C_DRIVE, A_DRIVE, None_DRIVE ;R66 ;R93A endif ;support_only_C_boot ;R93 endif ;HDD_Boot_Selectable ;R88 ifdef CD_ROM ;R88 ifdef BOOT_FORM_A_CD_C ;R149 DB A_DRIVE, CD_DRIVE, C_DRIVE ;R149 else ;BOOT_FORM_A_CD_C ;R149 DB C_DRIVE, CD_DRIVE, A_DRIVE endif ;BOOT_FORM_A_CD_C ;R149 ifdef BOOT_FORM_CD_A_C ;R78 DB CD_DRIVE, A_DRIVE, C_DRIVE ;R78 else ;BOOT_FORM_CD_A_C ;R78 DB CD_DRIVE, C_DRIVE, A_DRIVE endif ;BOOT_FORM_CD_A_C ;R78 endif ;CD_ROM ;R88 ;R28 end ;R88 start ifdef HDD_Boot_Selectable DB C_DRIVE, A_DRIVE, SCSI_DRIVE ;D,A DB C_DRIVE, A_DRIVE, SCSI_DRIVE ;E,A DB C_DRIVE, A_DRIVE, SCSI_DRIVE ;F,A DB SCSI_DRIVE, A_DRIVE, C_DRIVE ;SCSI,A,C DB SCSI_DRIVE, C_DRIVE, A_DRIVE ;SCSI,C,A endif ;HDD_Boot_Selectable ;R88 end DB C_DRIVE, None_DRIVE, None_DRIVE ;R93A ;R110 start ifdef WINCOM_boot_item DB A_DRIVE, CD_DRIVE, SCSI_DRIVE ;A,CDROM,SCSI DB C_DRIVE, CD_DRIVE, SCSI_DRIVE ;C,CDROM,SCSI endif ;WINCOM_boot_item ;R110 end ;R115A start ifdef LS120_SUPPORT ATAPI_Boot equ 1 endif ;LS120_SUPPORT ifdef IOMEGA_ZIP_Support ATAPI_Boot equ 1 endif ;IOMEGA_ZIP_Support ifdef ATAPI_Boot DB LS120_DRIVE, C_DRIVE, None_DRIVE endif ;ATAPI_Boot ;R115A end ;R115Aifdef LS120_SUPPORT ;R115 ;R115A DB LS120_DRIVE, C_DRIVE, None_DRIVE ;R115 ;R115Aendif ;LS120_SUPPORT ;R115 ;R162 - start ; Buffer for recording Bootstrap Entry Tables (BEV) of network device ; Support maximum 8 devices with BEV. public BootEntryTbl public BootEntryEnd BootEntryTbl label near dd 8 dup (0) ;segment + offset address of BEV BootEntryEnd label near ;Function : Try booting from devices with Bootstrap Entry Vectors(BEV) ;Input : DS - G_RAM ;Output : none assume DS:G_RAM BootFromBEVs proc near ;Booting from BEV devices , normally for network cards ;The boot ROM of Intel 559 use BEV structure for booting mov si, offset BootEntryTbl ;BEV table RunNextBev: mov ebx, dword ptr cs:[si] ;get BEV tables or ebx, ebx ;BEV existed / jz short NoBevTbl push si mov si, offset ROM_MODULE_OFFSET mov dword ptr [si], ebx call dword ptr [si] ;execute BEV pop si add si, 4 ;next table cmp si, offset BootEntryEnd ;last BEV table ? jne short RunNextBev NoBevTbl: ret BootFromBEVs endp ;R162 - end align 4 ;R25 PUBLIC INT_19S INT_19S PROC NEAR mov ax,G_RAM mov ds,ax assume ds:G_RAM cli mov word ptr ds:[Disk_Parm_Ptr], offset cs:FDC_PARS mov word ptr ds:[Disk_Parm_Ptr+2],cs sti ;R125B ;R125 - start ;R125B ifdef LAN_BOOT_SUPPORT ;R125B ;Boot from INT 18H first if user enable in CMOS setup ;R125B test byte ptr ds:SYSTEM_FLAG,BOOT_LAN ;boot LAN ? ;R125B jz short NoInt18Hooked ;R125B ;R125B ;check if INT 18H hooked by other ROMs ;R125B cmp word ptr ds:[Int18],offset cs:Int18_Hdlr ;R125B jne short YesTryInt18 ;R125B ;R125B push ax ;R125A ;R125B mov ax,cs ;INT 18 hooked ? ;R125B cmp word ptr ds:[Int18+2],ax ;R125B pop ax ;R125A ;R125B je short NoInt18Hooked ;R125B ;R125B YesTryInt18: ;R125B int 18H ;R125B NoInt18Hooked: ;R125B endif; LAN_BOOT_SUPPORT ;R125B ;R125 - end ;R28 start ;R43ifdef CD_ROM ;R43 push ax ;R43 test byte ptr G_RAM:[CDROM_EMUL_HEAD],0fh ;R43 jz No_CDROM_Bootable ;R43 mov es,ax ;R43 mov al,G_RAM:[CDROM_EMUL_HEAD] ;R43 mov G_RAM:[CDROM_ALLOCATE],al ;R43 mov dword ptr G_RAM:[CDROM_EMUL_START_SECTOR],0 ;R43 mov word ptr G_RAM:[CDROM_EMUL_CYL_SEC],0ffffh ;R43 mov byte ptr G_RAM:[CDROM_EMUL_HEAD],16 ;R43 inc byte ptr G_RAM:[NumHDSKS] ;R43 mov ax,201h ;R43 mov bx,offset Boot ;R43 mov cx,6 ;R43 mov dx,180h ;R43 int 13h ;R43 jc CDROM_Fail ;R43 cmp dword ptr es:[bx+1],'00DC' ;R43 jne CDROM_Fail ;R43 cmp byte ptr es:[bx+5],'1' ;R43 jne CDROM_Fail ;R43 mov eax,es:[bx+47h] ;R43 call Xlat_CDsec_CHS ;R43 mov ax,201h ;R43 mov dl,80h ;R43 int 13h ;R43 jc CDROM_Fail ;R43 mov ax,es:[bx] ;R43 cmp al,1 ;Header ID,must be 1 ;R43 jne CDROM_Fail ;R43;--- Platform ID --- ;R43AT_80x86 EQU 0 ;R43Power_PC EQU 1 ;R43Mac EQU 2 ;R43Comp_Platform: ;R43 cmp ah,AT_80x86 ;compare Platform ID ;R43 je short Scan_bootable ;R43@@: ;R43 add bx,20h ;R43 cmp bx,offset Boot + 800h ;R43 jae CDROM_Fail ;R43 mov ax,es:[bx] ;R43Comp_Header: ;R43 cmp al,90h ;R43 je short Comp_Platform ;R43 cmp al,91h ;R43 je short Comp_Platform ;R43 jmp short @B ;R43Scan_bootable: ;R43 add bx,20h ;R43 cmp bx,offset Boot + 800h ;R43 jae CDROM_Fail ;R43 mov ax,es:[bx] ;R43 cmp al,88h ;Is Bootable image? ;R43 jne short Comp_Header ;No,jump ;R43 mov edx,es:[bx+8] ;R43 mov ds:CDROM_EMUL_START_SECTOR,edx ;R43 and ah,0fh ;R43 cmp ah,1 ;R43 je short Floppy_120MB ;R43 cmp ah,2 ;R43 je short Floppy_144MB ;R43 cmp ah,3 ;R43 je short Floppy_288MB ;R43 cmp ah,4 ;Is emulate HD drive? ;R43 je short HDD_Drive ;R43 jmp short CDROM_Fail ;R43Floppy_120MB: ;R43 mov byte ptr ds:[CDROM_EMUL_CYL_SEC],0fh ;R43 jmp short @F ;R43Floppy_144MB: ;R43 mov byte ptr ds:[CDROM_EMUL_CYL_SEC],12h ;R43 jmp short @F ;R43Floppy_288MB: ;R43 mov byte ptr G_RAM:[CDROM_EMUL_CYL_SEC],24h ;R43@@: ;R43 mov byte ptr G_RAM:[CDROM_EMUL_CYL_SEC+1],50h ;R43 sub byte ptr G_RAM:[CDROM_ALLOCATE],4 ;R43 mov byte ptr G_RAM:CDROM_EMUL_HEAD,2 ;R43 jmp short No_CDROM_Bootable ;R43HDD_Drive: ;R43 mov ax,201h ;R43 mov bx,offset Boot ;R43 mov cx,1 ;R43 mov dx,80h ;R43 int 13h ;R43 add bx,1beh ;R43@@: ;R43 cmp word ptr es:[bx],0aa55h ;R43 je short CDROM_Fail ;R43 test byte ptr es:[bx],80h ;R43 jnz short @F ;R43 add bx,10h ;R43 jmp @B ;R43@@: ;R43 mov al,es:[bx+5] ;R43 inc al ;R43 mov ds:CDROM_EMUL_HEAD,al ;R43 mov ax,es:[bx+6] ;R43 mov ds:CDROM_EMUL_CYL_SEC,ax ;R43 jmp short No_CDROM_Bootable ;R43CDROM_Fail: ;R43No_CDROM_Bootable: ;R43 pop ax ;R43endif ;CD_ROM ;R28 end new_dsk: ;R156 mov dx,ax ; (ax is 0) ;R156 mov es,ax ; set to load at 0:offset Boot ;R156 ;R156 mov bx,offset Boot ;R156 mov cx,1 ; set to read one sector ; mov al,CMOS_AWARD_CK NMI_ON ; get CMOS byte with boot indicator ; call Get_CMOS ; test al,HARD_DISK_FIRST ; check try hard first ;R79 mov si,offset BootSeq_Item ;R79 call GetItem_Cmos ;R79 - start ;R156 mov al,ds:[BootSel] ;get boot sequence ;R79 - end ;R28 start ;R156 xor ah,ah ;R156 mov si,ax ;R156 shl si,1 ;si = si*3 ;R156 add si,ax ;--------- ;R156 add si,offset Boot_Seq_Drive ;R28 end ;R28 or al,al ;R28 jz short do_boot ; skip if floppy first ;R28 mov dl,80h ; else setup for hard first ;R28 do_boot: ;R156 mov dl,cs:[si] ;R28 xor dl,dl ;R156 call try_boot ; try boot load on first device ;R156 jnc good_load ; skip if load good ;R28 xor dl,80h ; get to next device ;R156 mov dl,cs:[si+1] ;R28 mov dl,1 ;R156 call try_boot ; try boot load on second device ;R156 jnc good_load ; skip if load good ;R88;R28 start ;R88ifdef CD_ROM ;R156 mov dl,cs:[si+2] mov dl,2 ;R156 call try_boot ;R156 jnc good_load ;R88endif ;CD_ROM ;R88;R28 end jmp hang ; else skip to handle bad load align 4 ;R25 try_boot proc near ;R156 push si ;R28 ;R156 start mov ax,G_RAM ;get DS=G_RAM mov ds,ax ; movzx ax,byte ptr ds:[BootSel];get boot sequence mov si,ax shl si,1 ;si = si*3 add si,ax ;--------- add si,offset Boot_Seq_Drive xor dh,dh add si,dx mov dl,cs:[si] ;get boot drive number ;R156 end cmp dl,None_Drive ;R66 je load_failed ;R66 ;R88 start ;R164 ifdef HDD_Boot_Selectable ;R164 and byte ptr [CDROM_ALLOCATE],not Enable_SCSI_Boot ;R164 cmp dl,SCSI_Drive ;R164 jne short @F ;R164 cmp byte ptr cs:[SCSI_Drive_Max_Num],80h ;SCSI present ? R88A ;R164 jbe Load_Failed ;no SCSI drive R88A ;R164 or byte ptr [CDROM_ALLOCATE],Enable_SCSI_Boot ;R164 mov dl,C_DRIVE ;R164 @@: ;R164 endif ;HDD_Boot_Selectable ;R88 end mov si,3 ; setup for three retries xor di,di ; assume floppy boot try ;R10 or dl,dl ; boot from HDD? ;R10 js short @F ; yes ;R10 mov al,10h NMI_ON ; FDD CMOS value ;R10 call Get_CMOS ;R10 test al,11110000b ;R10 jz short Load_Failed ;R10 @@: ;R115A start mov al,10h NMI_ON ; FDD CMOS value call Get_CMOS ifdef ATAPI_Boot test al,11110000b jz short No_FloppyA or byte ptr [ATAPI_Byte],8 No_FloppyA: endif ;ATAPI_Boot ;R115A end or dl,dl ; check hard disk boot ;R28 jns short try_again ; skip if not for floppy ;R28 start js short @F ;R60 start ;R115A mov al,10h NMI_ON ; FDD CMOS value ;R115A call Get_CMOS test al,11110000b jnz short Floppy_Exist test byte ptr [ATAPI_Byte],4 ;R97 jnz short Floppy_Exist ;R97 cmp word ptr [int13],offset HRDSKIO jne short Floppy_Exist cmp word ptr [int40],offset DSK_VECT je Load_Failed Floppy_Exist: ;R60 end ;R120 start ifdef Support_DriveA_Boot_Permit cmp dl,A_DRIVE jne short Not_DriveA_Boot mov al,DriveA_Boot_Permit_CMOS NMI_OFF call Get_Cmos test al,DriveA_Boot_Permit_CMOS_Mask jz Load_Failed Not_DriveA_Boot: endif ;Support_DriveA_Boot_Permit ;R120 end ;R115 start ;R115Aifdef LS120_SUPPORT ;R115A cmp dl,A_DRIVE ;R115A jne short Not_FloppyA_boot ;R115A test al,11110000b ;R115A jz short Not_LS120_boot ;R115A or byte ptr [ATAPI_Byte],8 ;R115ANot_FloppyA_boot: ifdef ATAPI_Boot ;R115A cmp dl,LS120_DRIVE jne short Not_LS120_boot test byte ptr [ATAPI_Byte],4 ;R145 jz load_failed ;R145 and byte ptr [ATAPI_Byte],not 8 mov dl,A_DRIVE Not_LS120_boot: ;R115Aendif ;LS120_SUPPORT endif ;ATAPI_Boot ;R115A ;R115 end ifdef CD_ROM mov al,G_RAM:[CDROM_ALLOCATE] and al,0fh shr al,2 cmp al,1 ;emulate Drive A? ;R43 jne short try_again jne try_again ;R43 inc dl endif ;CD_ROM ;R43 jmp short try_again jmp try_again ;R43 @@: ;R28 end inc di ; else signal hard boot, (tested by Check_Boot_Record) ;R28 start ifdef CD_ROM ;R43 cmp dl,80h ;R43 jne short @F ;R43 start cmp dl,80h jne Not_from_CDROM test byte ptr G_RAM:[CDROM_EMUL_HEAD],0fh jz No_CDROM_Bootable pusha push es push ds mov ax,G_RAM ;R97 mov es,ax test byte ptr G_RAM:[CDROM_ALLOCATE],0fh jnz short @F mov al,G_RAM:[CDROM_EMUL_HEAD] ;;R123 mov G_RAM:[CDROM_ALLOCATE],al and al,0fh ;R123 and G_RAM:[CDROM_ALLOCATE],0f0h ;R123 or G_RAM:[CDROM_ALLOCATE],al ;R123 inc byte ptr G_RAM:[NumHDSKS] @@: ;R52A start ifndef NO_CDROM_BOOT_MESSAGE ;R78 push ds push es mov di,CD_ROM_TEMP_SEG mov es,di mov di,27*2 - CD_Boot_Str0_len ;R53 mov cx,CD_Boot_Str0_len ;R53 push cs ;R53 pop ds ;R53 lea si,CD_Boot_Str0 ;R53 rep movsb ;R53 mov bp,27*2 - CD_Boot_Str0_len ;R53 ;R68 mov cx,Model_Number_Len ;R53 ;R68 add cx,CD_Boot_Str0_len ;R53 mov cx,CD_Boot_Str0_len ;R68 call Display_str ;R53 ;R68 mov di,27*2 ;R53 push cs ;R53 pop ds ;R68Found_Loop: ;R68 lea si,Special_CDROM_Drive ;R68 mov cx,Special_CDROM_Len0 ;R68 rep cmpsb ;R68 jz short Found_It ;R68 cmp di,27*2+Model_Number_Len-Special_CDROM_Len0 ;R68 jbe short Found_Loop ;R68Found_It: pop es pop ds endif ;NO_CDROM_BOOT_MESSAGE ;R78 ;R68 jnz short @F ;R68 or byte ptr G_RAM:[CDROM_ALLOCATE],Special_CDROM_Bit @@: ;R52A end mov dword ptr G_RAM:[CDROM_EMUL_START_SECTOR],0 mov word ptr G_RAM:[CDROM_EMUL_CYL_SEC],0ffffh ;R123C mov byte ptr G_RAM:[CDROM_EMUL_HEAD],16 mov byte ptr G_RAM:[CDROM_EMUL_HEAD],255 ;R123C ;R96 mov cx,800h ;R53 ;R97 mov cx,2000h ;R96 ;R123A mov cx,0a000h ;R123 ;R123A test G_RAM:[CDROM_ALLOCATE],Special_CDROM_Bit ;R123 ;R123A jnz @F ;R123 ;R123A start ;R123D test G_RAM:[CDROM_ALLOCATE],Special_CDROM_Bit ;R123D jz @F xor cx,cx ;R123B mov bx,1 ;R123D mov bx,5 ;R123B 5*2.5 =12.5 sec ;R150 movzx bx,byte ptr DGROUP:[CDROM_Boot_Delay] ;R123D ;R150 or bl,bl ;R123D ;R150 jz short @F ;R123D ;R150 call WAIT_REFRESH ;R123D mov cx,0a000h ;R123B more loop to read boot data ;R123D jmp short Spec_CDROM ;R123B ;R150@@: ;R123A end ;R123D mov cx,800h ;R97 ;R150 xor cl,cl ;R123D ;R150 mov ch,byte ptr DGROUP:[CDROM_Boot_loop] ;R123D ;R159 mov cx,80 ;R150 mov cx,400h ;R159 ;R150Spec_CDROM: ;R123B @@: ;R53 push cx ;R53 mov ax,201h mov bx,offset Boot mov cx,6 mov dx,180h ;R57 int 13h pushf ;R57 call far ptr HRDSKIO ;R57 ;R53 jc CDROM_Fail pop cx ;R53 jnc short @F ;R53 cmp ah,32H ;R127 ;R127 Media type not supported by drive je short CDROM_Fail_0 ;R127 loop short @B ;R53 CDROM_Fail_0: ;R127 jmp CDROM_Fail ;R53 @@: ;R53 cmp dword ptr es:[bx+1],'00DC' jne CDROM_Fail cmp byte ptr es:[bx+5],'1' jne CDROM_Fail mov eax,es:[bx+47h] call Xlat_CDsec_CHS ;read booting catalog to CD_ROM_TEMP_SEG:CD_ROM_TEMP_OFF mov bx,CD_ROM_TEMP_SEG mov es,bx mov bx,CD_ROM_TEMP_OFF mov ax,201h mov dl,80h ;R57 int 13h pushf ;R57 call far ptr HRDSKIO ;R57 jc CDROM_Fail cmp byte ptr es:[bx],1 ;Header ID,must be 1 jne CDROM_Fail ;R44A mov di,CD_ROM_TEMP_SEG ;R44A mov es,di ;R44A mov di,200h ;R44A mov dl,G_RAM:[CDROM_ALLOCATE] ;R44A and dl,3 ;R44A add dl,80h ;R44A Post_func_call Auto_IDE_Detect ;R53 mov di,27*2 - CD_Boot_Str0_len ;R53 mov cx,CD_Boot_Str0_len ;R53 push cs ;R53 pop ds ;R53 lea si,CD_Boot_Str0 ;R53 rep movsb ;R53 add di,Model_Number_Len ;R53 lea si,CD_Boot_Str1 ;R53 mov cx,CD_Boot_Str1_len ;R53 rep movsb ;R53 ;R53 mov bp,27*2 - CD_Boot_Str0_len ;R53 mov cx,Model_Number_Len ;R53 add cx,CD_Boot_Str0_len ;R53 add cx,CD_Boot_Str1_len ;R53 call Display_str ifndef NO_CDROM_BOOT_MESSAGE ;R78 push es ;R53 push cs ;R53 pop es ;R53 lea bp,CD_Boot_Str1 ;R53 mov cx,CD_Boot_Str1_len ;R53 call Display_str ;R53 pop es ;R53 endif ;NO_CDROM_BOOT_MESSAGE ;R78 mov bx,CD_ROM_TEMP_SEG mov es,bx mov bx,CD_ROM_TEMP_OFF mov di,TEMP_OFF mov dword ptr es:[di+0b0h],'.0 ' mov dword ptr es:[di+0b4h],' DH ' mov ah,es:[bx+1] ;--- Platform ID --- AT_80x86 EQU 0 Power_PC EQU 1 Mac EQU 2 Comp_Platform: cmp ah,AT_80x86 ;compare Platform ID je short Scan_bootable @@: add bx,20h cmp bx,CD_ROM_TEMP_OFF + 800h jae Scan_over mov ax,es:[bx] Comp_Header: cmp al,90h je short Comp_Platform cmp al,91h je short Comp_Platform jmp short @B Scan_bootable: add bx,20h cmp bx,CD_ROM_TEMP_OFF + 800h jae Scan_over mov ax,es:[bx] cmp al,88h ;Is Bootable image? jne short Comp_Header ;No,jump mov dl,es:[bx+4] ;get System Type mov es:[di],bx add di,2 or ah,ah ;R81 jz Scan_over ;R81 ;show item push bx mov bp,TEMP_OFF+0b0h inc byte ptr es:[bp+2] mov byte ptr es:[bp+5],'H' mov bx,TEMP_OFF+0b7h and ah,0fh cmp ah,4 je short Emulate_HDD ;emulate as HDD push bp add bp,5 mov byte ptr es:[bp],'F' add bp,2 mov al,ah dec al mov bl,7 mul bl lea bx,Floppy_Str add bx,ax mov cx,7 @@: mov al,cs:[bx] inc bx inc bp mov es:[bp],al loop short @B mov bx,bp pop bp Emulate_HDD: mov dword ptr es:[bx+1],'syS ' mov dword ptr es:[bx+5],' met' mov dword ptr es:[bx+9],'epyT' mov dword ptr es:[bx+13],' (-' mov byte ptr es:[bx+17],')' mov dh,dl and dh,0fh cmp dh,9 jbe short @F add dh,7 @@: shr dl,4 cmp dl,9 jbe short @F add dl,7 @@: add dx,3030h mov es:[bx+15],dx mov byte ptr es:[bx+18],0dh mov byte ptr es:[bx+19],0ah mov cx,bx sub cx,bp add cx,20 call Display_str pop bx jmp scan_bootable Scan_over: pop ds cmp di,TEMP_OFF je Scan_image_OK cmp di,TEMP_OFF+2 ;Is single image? jne short @F ;No,jump mov di,TEMP_OFF jmp short Boot_Start @@: push es push cs pop es ;select item Select_again: lea bp,Option_Str mov cx,Option_Str_len call Display_str xor ah,ah int 16h cmp al,0dh jne short Not_Enter_Key mov al,'1' jmp short Select_Done Not_Enter_Key: mov ah,9 mov bx,7 mov cx,1 int 10h cmp al,'0' jne short Not_0_Key mov al,G_RAM:[CDROM_ALLOCATE] mov G_RAM:[CDROM_EMUL_HEAD],al mov byte ptr G_RAM:[CDROM_ALLOCATE],0 lea bp,CD_Boot_Str1 mov cx,2 call Display_str pop es jmp Scan_image_OK Not_0_Key: cmp al,'1' jb short Select_again cmp al,'9' ja short Select_again Select_Done: xor ah,ah sub al,'1' shl ax,1 mov bx,TEMP_OFF add bx,ax cmp bx,di jae short Select_again mov di,bx ;save bx to di lea bp,CD_Boot_Str1 mov cx,2 call Display_str pop es ;Get bootable image in CD-ROM , check which boot mode ! Boot_Start: mov bx,es:[di] ;get section header entry mov ah,es:[bx+1] ;boot media type mov edx,es:[bx+8] ;start address of virtual ;disk mov ds:CDROM_EMUL_START_SECTOR,edx and ah,0fh ;bit7-5 reserved cmp ah,1 ;emulate 1.2Mb ? ;R81A je short Floppy_120MB je Floppy_120MB ;R81A cmp ah,2 ;emulate 1.44b ? ;R81A je short Floppy_144MB je Floppy_144MB ;R81A cmp ah,3 ;emulate 2.88Mb ? ;R81A je short Floppy_288MB je Floppy_288MB ;R81A cmp ah,4 ;emulate HD drive? ;R81A je short HDD_Drive je HDD_Drive ;R81A ;R81 start or ah,ah ;none emulation ? jnz Scan_image_OK ;no ;R88;R81A start ;R88 push es ;R88 push bx ;R88 CALL F000_Shadow_W ;R88 mov word ptr cs:[Int13_original_address+2],0ffffh ;R88 cmp word ptr G_RAM:[13h*4+2],0f000h ;int 13h segment at 0F000h segment ;R88 je short @F ;Yes,dont replace ;R88 mov ax,G_RAM:[13h*4+2] ;get int 13h segment ;R88 mov word ptr cs:[Int13_original_address+2],ax ;save old int 13h address ;R88 mov ax,G_RAM:[13h*4] ;R88 mov word ptr cs:[Int13_original_address],ax ;R88 mov ax,offset dgroup:hrdskio ;replace new int 13h address ;R88 mov G_RAM:[13h*4],ax ;R88 mov word ptr G_RAM:[13h*4+2],0f000h ;R88@@: ;R88 CALL F000_Shadow_R ;R88 pop bx ;R88 pop es ;R88;R81A end mov al,es:[bx+6] ;yes, get sector count mov bx,es:[bx+2] ;get load segment or bx,bx ;use segment 7c0H if zero jnz short @F mov bx,7c0h ;traditional segment @@: mov es,bx ;setup segment to load xor bx,bx ;set buffer offset to zero mov cx,1 ;sector No. 1 mov ah,2 ;read sector mov dx,CDROM_EMUL_NUM ;get no emulation drive NO. and byte ptr G_RAM:[CDROM_ALLOCATE],0f3h or byte ptr G_RAM:[CDROM_ALLOCATE],(NO_EMUL shl 2) pushf ;call INT 13H to read data call far ptr HRDSKIO dec byte ptr G_RAM:[NumHDSKS] ;fix 40:75 to correct drive number ;R98 start ;R98A start cmp word ptr G_RAM:[13h*4+2],0f000h ;int 13h segment at 0F000h segment je short @F ;Yes,dont replace push es pusha push ds call F000_Shadow_W pop ds mov eax,G_RAM:[13h*4] ;get int 13h segment mov cs:[Int13_original_address],eax ;save old int 13h address push ds call F000_Shadow_R pop ds popa pop es ;R98A end mov ax,offset dgroup:hrdskio ;replace old int 13h address mov G_RAM:[13h*4],ax mov word ptr G_RAM:[13h*4+2],0f000h ;R98 end @@: ;R98A push es push bx retf ;jump to ES:BX ;R81 end ;R81 jmp short Scan_image_OK Floppy_120MB: mov byte ptr ds:[CDROM_EMUL_CYL_SEC],0fh jmp short @F Floppy_144MB: mov byte ptr ds:[CDROM_EMUL_CYL_SEC],12h jmp short @F Floppy_288MB: mov byte ptr G_RAM:[CDROM_EMUL_CYL_SEC],24h @@: mov byte ptr G_RAM:[CDROM_EMUL_CYL_SEC+1],50h sub byte ptr G_RAM:[CDROM_ALLOCATE],4 mov byte ptr G_RAM:CDROM_EMUL_HEAD,2 ;R97 start test byte ptr G_RAM:ATAPI_Byte,00001000b jnz short ARMD_Is_B or byte ptr G_RAM:ATAPI_Byte,00001000b ;Set to B add G_RAM:HARDWARE,40h jmp short Scan_image_OK ARMD_Is_B: and byte ptr G_RAM:ATAPI_Byte,11110011b ;Set to none ;R97 end jmp short Scan_image_OK HDD_Drive: mov ax,201h mov bx,offset Boot mov cx,1 mov dx,80h int 13h add bx,1beh @@: cmp word ptr es:[bx],0aa55h je short Scan_image_OK test byte ptr es:[bx],80h jnz short @F add bx,10h jmp short @B @@: mov al,es:[bx+5] inc al mov ds:CDROM_EMUL_HEAD,al mov ax,es:[bx+6] mov ds:CDROM_EMUL_CYL_SEC,ax jmp short Scan_image_OK CDROM_Fail: ifndef NO_CDROM_BOOT_MESSAGE ;R78 push cs ;R53 pop es ;R53 lea bp,CD_Boot_Str2 ;R53 mov cx,CD_Boot_Str2_len ;R53 call Display_str ;R53 endif ;NO_CDROM_BOOT_MESSAGE ;R78 pop ds ;R98 start mov al,G_RAM:[CDROM_ALLOCATE] mov G_RAM:[CDROM_EMUL_HEAD],al mov byte ptr G_RAM:[CDROM_ALLOCATE],0 dec byte ptr G_RAM:[NumHDSKS] pop es popa jmp short load_failed ;R98 end Scan_image_OK: pop es popa No_CDROM_Bootable: ;R43 end mov al,G_RAM:[CDROM_ALLOCATE] and al,0fh jz short load_failed shr al,2 cmp al,1 ;emulate Drive A? jne short try_again xor di,di ;R117 Set CDROM emul Floppy for ;R117 "CHECK_BOOT_RECORD" subroutine sub dl,80h jmp short try_again Not_from_CDROM: ;R43 ;R43@@: cmp dl,81h ;R43 jne short tt0 jne short tt0 ;R43 mov al,G_RAM:[CDROM_ALLOCATE] and al,0fh shr al,2 cmp al,2 ;Is emulate C? je short @F ;Yes,jump dec dl ;CDROM emulate drive C so DL=80h (from HDD boot) cmp byte ptr G_RAM:[NumHDSKS],0 ;R41 ;R43 je short load_failed ;R41 ;R43 jmp short tt0 ;R41 jne short tt0 ;R43 jmp short load_failed ;R43 @@: cmp byte ptr G_RAM:[NumHDSKS],1 ;R43 jbe short load_failed jbe short load_failed ;R43 tt0: else ;CD_ROM ;R28 end mov al,0eh NMI_ON ; set for read CMOS call Get_CMOS test al,FIXED_STATUS ; check for error initing hard disk jnz short load_failed ; skip if so to fail endif ;CD_ROM ;R28 try_again: xor ax,ax int 13h ; reset disk jc short try_fail mov ax,0201h ; read boot record ;R156 start mov bx,G_RAM mov es,bx ; set to load at 0:offset Boot mov bx,offset Boot ;buffer offset mov cx,1 ;cylinder = 0 and sector = 1 xor dh,dh ;head = 0 ;R156 end int 13h jnc short load_good cmp ah,80h je short load_failed try_fail: dec si test si,0fffh ;R63 jnz short try_again ; go again for all retries ;R05C load_failed: ;R63 start ifdef Support_B_Drive_Boot or dl,dl jnz short Not_Floppy_Boot test si,8000h jnz short @F mov si,8003h xor byte ptr G_RAM:[FDD_VERIFY_CMD_FLAG],SWAP_DRIVE jmp short try_again ;boot again for another drive @@: xor byte ptr G_RAM:[FDD_VERIFY_CMD_FLAG],SWAP_DRIVE Not_Floppy_Boot: endif ;Support_B_Drive_Boot ;R63 end ;R156 pop si ;R28 stc ; signal boot load failure ret load_good: call Check_Boot_Record jc short try_fail ; skip on failure to try again ;R28 start ifdef CD_ROM mov al,G_RAM:[CDROM_ALLOCATE] and al,0fh shr al,2 cmp al,2 ;R37 je short Emulate_C je short Emulate_C ;R37 cmp al,1 ;Emulate Drive A ;R37 jne short try_boot_OK ;No,jump jne short try_boot_OK ;R37 cmp dl,1 ;R37 je short Disable_CD je Disable_CD ;R37 cmp dl,80h ;R37 je short Disable_CD je Disable_CD ;R37 dec byte ptr G_RAM:[NumHDSKS] MOV AL,FLOPPY_TYPE NMI_OFF CALL GET_CMOS test al,0f0h ;R37 jz short @F ;R43 jz short Boot_from_CD ;R37 jz short try_boot_OK ;R43 or byte ptr G_RAM:[HARDWARE],40h ;R37 @@: ;R37 start ;R43Boot_from_CD: ;R44A;R43 mov di,2000h ;R44A;R43 mov es,di ;R44A;R43 mov di,200h ;R44A;R43 mov dl,G_RAM:[CDROM_ALLOCATE] ;R44A;R43 and dl,3 ;R44A;R43 add dl,80h ;R44A;R43 Post_func_call Auto_IDE_Detect ;R43 mov di,27*2 - CD_Boot_Str0_len ;R43 mov cx,CD_Boot_Str0_len ;R43 push cs ;R43 pop ds ;R43 lea si,CD_Boot_Str0 ;R43 rep movsb ;R43 add di,Model_Number_Len ;R43 lea si,CD_Boot_Str1 ;R43 mov cx,CD_Boot_Str1_len ;R43 rep movsb ;R43 ;R43 mov ah,3 ;R43 xor bh,bh ;R43 int 10h ;R43 ;R43 mov ax,1301h ;R43 mov bp,27*2 - CD_Boot_Str0_len ;R43 mov cx,Model_Number_Len ;R43 add cx,CD_Boot_Str0_len ;R43 add cx,CD_Boot_Str1_len ;R43 mov bx,7 ;R43 int 10h ;R37 end jmp short try_boot_OK Emulate_C: or dl,dl jz short Disable_CD ;R37 cmp dl,81h ;R37 jne short try_boot_OK cmp dl,80h ;R37 ;R43 je short Boot_from_CD ;R37 je short try_boot_OK ;R43 Disable_CD: test byte ptr G_RAM:[CDROM_ALLOCATE],0fh jz short try_boot_OK and byte ptr G_RAM:[CDROM_ALLOCATE],0f0h dec byte ptr G_RAM:[NumHDSKS] try_boot_OK: ;R136 clc endif ;CD_ROM ;R156ifndef No_Check_HDD_Active_Bit ;R152 ;R156 call HDD_Active ;R136 ;R156;R152 - start ;R156else; No_Check_HDD_Active_Bit ;R156 clc ;R156endif; No_Check_HDD_Active_Bit ;R156;R152 - end ;R156 pop si ;R156 start mov ax,cs ;get return segment mov G_RAM:[ROM_MODULE_SEG],ax ;set to G_RAM pop ax ;get return offset mov G_RAM:[ROM_MODULE_OFFSET],ax ;set to G_RAM jmp far ptr Boot ;go to boot code ;R156 end ;R28 end ret ; return boot load good, (carry clear) try_boot endp ;R156ifndef No_Check_HDD_Active_Bit ;R152 ;R156;R136 start ;R156;============================================================================ ;R156; Test HDD active bit of partition table set or not ;R156; Input : DL = 80h or larger test it otherwise don't check and return NC ;R156; DS:[BOOT] = boot record ;R156; Output : C flag = NC : found it or not HDD ;R156; set : not found ;R156;============================================================================ ;R156HA_Err_msg: db 'Not found any [active partition] in HDD',0ah,0dh ;R156HA_Err_msg_Len equ $ - offset HA_Err_msg ;R156 ;R156HDD_Active: ;R156 push es ;R156 pusha ;R156;R136A cmp dl,80h ;check HDD? ;R156;R136A jb short HA_Normal_Ret ;No,skip ;R156 test dl,80h ;R136A check HDD? ;R156 jz short HA_Normal_Ret ;R136A No,skip ;R156 mov bx,offset Boot+1beh ;point to first partition offset ;R156HA_check_loop: ;R156 test byte ptr ds:[bx],80h ;active set? ;R156 jnz short HA_Normal_Ret ;Yes,jump to return ;R156 add bx,10h ;next partition ;R156;R136A cmp bx,1feh ;final? ;R156 cmp bx,offset Boot+1feh ;R136A final? ;R156 jne short HA_check_loop ;No,goto loop ;R156 push cs ;R156 pop es ;R156 lea bp,HA_Err_msg ;R156 mov cx,HA_Err_msg_Len ;R156 call Display_str ;show error message ;R156 stc ;Set error flag ;R156 jmp short HA_Exit ;R156HA_Normal_Ret: ;R156 clc ;no error ;R156HA_Exit: ;R156 popa ;R156 pop es ;R156 ret ;R156;R136 end ;R156endif; No_Check_HDD_Active_Bit ;R152 hang: call BootFromBEVs ;boot from BEVs ;R162 cmp word ptr ds:[Int18],offset cs:Int18_Hdlr jne short do_18 mov ax,cs cmp word ptr ds:[Int18+2],ax je short hang_it DO_18: int 18h ; do lan/ROS boot hang_it: mov si,offset cs:Bad_Disk_Msg ;M01 - starts ifdef RPB_BOOT_FAIL_TRIGGER push cs ;push code segment pop ds ;point DS to CS call rpbf_preboot_agent_trigger ;connect with Preboot Agent on failure else ;RPB_BOOT_FAIL_TRIGGER ;M01 - ends call Wr_Str_TTY endif ;RPB_BOOT_FAIL_TRIGGER ;M01 endless: xor ah,ah int 16h ; wait for return key cmp ah,1ch jne short endless mov al,ds:Con_Mode ; clear error message xor ah,ah int 10h xor ax,ax ; g_ram jmp new_dsk ;R156good_load: ;R156;R100 success: ;R156 jmp far ptr Boot ; go to boot code INT_19S ENDP PAGE ;[]==============================================================[] ; ;CHECK_BOOT_RECORD: ; ; Checks to see if boot record read from disk or diskette ; is valid. ; ; ;Saves: NONE ; ;Entry: DI 0 = floppy, 1 = fixed ; DS:BOOT boot record ; ;Exit: C Set if invalid boot record ; ;Author: Award ;Date: 04/18/90 ; ; Name | Date | Description ; --------------------------------------------------------------- ; TIM | 18-Apr-90 | Initial revision ; ;[]==============================================================[] align 4 ;R25 public CHECK_BOOT_RECORD CHECK_BOOT_RECORD PROC NEAR push bx push cx or di,di ; floppy or hard disk ? jz short check_fdu mov ax,word ptr ds:[Boot + 510] ; chksum of fixed disk partition cmp ax,0aa55h ; record correct je short cbr_exit ; exit with carry clear. jmp short cbr_fail ; stc and exit. check_fdu: ;R122 - start ifdef SPECIAL_FDD_BOOT_CHECK cmp word ptr ds:[Boot+1FEH],0DCABH ; check special signature jne short cbr_fail ; then its invalid. endif; SPECIAL_FDD_BOOT_CHECK ;R122 - end mov ax,word ptr ds:[Boot] ; read the 1st word cmp al,5 ; if 1st byte is an add op jbe short cbr_fail ; then its invalid. mov cx,8 ; check for formatted diskette xor bx,bx ; by seeing if 1st 9 are same. ALIGN 4 check_formatted: inc bx ; have a fill pattern if they inc bx ; haven't been written to.) cmp ax,word ptr ds:Boot[bx] loope short check_formatted clc ; success jne short cbr_exit cbr_fail: stc cbr_exit: pop cx pop bx ret CHECK_BOOT_RECORD ENDP SUBTTL ;[]==============================================================[] ; ;C_MOD_CK: ; ; Checks for and invokes Award modular code units. ; ; ; ;Saves: NONE ; ;Entry: CS:BX Points to modular code unit table (0FFFFh terminated) ;Exit: NONE ; ;Notes: 1. This implementation of the 8242 takes over one of the ; 40: COM port addresses. ; ;Author: Award ;Date: 04/18/90 ; ; Name | Date | Description ; --------------------------------------------------------------- ; TIM | 22-Apr-90 | Updatate for 4.0 ; ;[]==============================================================[] align 4 ;R25 PUBLIC C_MOD_CK C_MOD_CK PROC NEAR ; pusha ; save all registers, so code units can ; push ds ; can make free use of them. ; push es ; ;cmc_next: ; mov ax,cs:[bx] ; ; cmp ax,0ffffh ; end of table? ; je short cmc_exit ; ; inc bx ; inc bx ; point to next entry in table. ; ; push bx ; save bx, in case module destroys it. ; call ax ; call the module. ; pop bx ; recover pointer ; ; jmp short cmc_next ; ;cmc_exit: ; pop es ; restore registers. ; pop ds ; popa ret C_MOD_CK ENDP PAGE ;[]==============================================================[] ; ;R_MOD_CK: ; ; Checks for and invokes option ROMs. ; ; ; ;Saves: NONE ; ;Entry: BX Starting segment address. ; DX Ending segment address. ;Exit: NONE ; ;Notes: 1. This implementation of the 8242 takes over one of the ; 40: COM port addresses. ; ;Author: Award ;Date: 04/18/90 ; ; Name | Date | Description ; --------------------------------------------------------------- ; ATQ | 11-12-90 | Deleted extra test for E000 ; TIM | 22-Apr-90 | Updatate for 4.0 ; ;[]==============================================================[] ; INPUT: BX=Starting segment address. ; DX=ending segment address. ; bx= bit 0, 1=1024k FSCAN ONLY ; OUTPUT: option roms called. ; PRESERVES: DS. All other registers may be destroyed by ROMS. ; align 16 PUBLIC R_MOD_CK R_MOD_CK PROC NEAR PUSH DS ;Deleted IFDEF FSCAN ;Deleted PUSH BX ;Deleted MOV BP,SP ; SAVE FOR PARAMETER SCAN ;Deleted AND BL,0FEH ; CLEAR BIT 0 ;Deleted ENDIF ; FSCAN CK1: PUSH DX ; saving ending address MOV DS,BX XOR SI,SI ; Signature check: If the bus is "floating" (no RAM, not pulled up), ; then data read from it will be decaying data previously fetched as ; opcodes, or I/O, or memory data. We can force this (decaying value) ; to a known state, noting that the Bus-Interface-Unit and Instruction- ; -Execution-Unit act in parallel, and that the BIU will try to totally ; load the prefetch queue after a jump. If immediately after a JMP, we ; place an opcode to read the target data (MOV), then follow that opcode ; with, say, NOPs (90H), it will happen that the MOV opcode's request ; for bus access will not be honored until several 90Hs are already read ; into the prefetch queue. And hence the 90Hs will be imposed on the ; floating bus, and read into the CPU as if it were the intended data. JMP short CHK_BUS ; purge prefetch queue ALIGN 4 ; purge prefetch queue CHK_BUS: MOV AX,[SI] ; get signature DB 18 DUP( 90H ) ; assert NOPs on bus CMP AX, 0AA55H JNE SHORT NXT_BLK MOV CL,[SI+2] CHK_IT: SHL CX,9 PUSH CX XOR AH,AH ; ah=accumulator ; CX HAS BYTE LENGTH FOR SHADOW CK2: CLD LODSB ADD AH,AL LOOP SHORT CK2 POP AX ; recover ROM length JNZ SHORT NXT_BLK ; if checksum is not zero, ; assume it is just a bus ; error, and continue. SHR AX,4 ;The following code fudges the value added to the Option ROM Current ; Address in BX to handle 64K Option ROMS or E000 page Option ROM. The ; 80h (64 * 2) gets expanded (multiplied by 512) and overflows CX to zero ; which gets pushed and then POPed into AX which would then get added to ; BX which would leave us pointed to where we begain which means we would ; find and initialize the ROM over and over. We now will look for a zero ; value in AX and fudge it to a value to indicate 64K ROM size. JNZ short calc_nxt_blk ; if AX is non-0 then go on mov ah,10h ; else the ROM is 64K so fudge AX calc_nxt_blk: ADD BX,AX XOR AX,AX MOV ES,AX MOV DI,OFFSET ROM_MODULE_OFFSET MOV WORD PTR ES:[DI][0], 3 MOV ES:[DI][2], DS ;Deleted IFDEF FSCAN ;Deleted PUSH BP ;Deleted ENDIF ; FSCAN ; PUSHF ; preserve direction, other flags ;R24 - start ifdef PCI_BUS ;Pass PCI parameters for ROM initialization mov cx,PCI_VGA_INFO[bp] ;save info in CX endif; PCI_BUS ;R24 - end ; DECNET card installation fix. ; Fudge stack so that it is at 0:3f8 when Option Rom is called (except ; when entrance to this proc has BX0=1, F000 SCAN, in which case SP=3XX). MOV AX, SP CMP AX, 400H JBE short SKIP_FUDGE MOV SP, 400H SKIP_FUDGE: PUSH AX PUSH BX push bp ;R158 ;R24 - start ifdef PCI_BUS ;Pass PCI parameters for ROM initialization mov ax,cx ;get inform. from CX endif; PCI_BUS ;R24 - end CALL DWORD PTR ES:[DI] pop bp ;R158 POP BX POP SP ; Restore original stack ; POPF ; restore flags. ;Deleted IFDEF FSCAN ;Deleted POP BP ;Deleted ENDIF ; FSCAN JMP SHORT CK_NEXT NXT_BLK: ;Deleted IFDEF FSCAN ;Deleted ADD BX,40H ;Deleted TEST WORD PTR [BP],1 ;Deleted JNZ SHORT CK_NEXT ;Deleted ADD BX,40H ;Deleted ELSE ADD BX,80H ;Deleted ENDIF ; FSCAN CK_NEXT: POP DX CMP BX,DX jae short ck_next_cont1 jmp short ck1 ck_next_cont1: ;Deleted IFDEF FSCAN ;Deleted POP BX ;Deleted ENDIF ; FSCAN POP DS RET R_MOD_CK ENDP ;[]==================================================================[] ; ; Procedure Name: SHADOW_DR ; ; Copy the cmos_drive( 48 and 49) parameters ; from BIOS stack to System Shadow Ram ; ; Saves: None ; ; Destroyed: ax ; ; Input: es - segment to copy ;R18 ; ; Output: None ; ; [Note]: ; ; 1. Shadow is supposed to be turned on before entry: ; ; Name | Date | Description ; ----------------------------------------------------------------- ; WC | 05/21/91 | Initial version ;[]==================================================================[] align 4 ;R25 public Type_To_DrvParm ;R42 Type_To_DrvParm: dw offset DGROUP:HDDC_ITEM,offset DGROUP:DRV0 db 1 dw offset DGROUP:HDDD_ITEM,offset DGROUP:DRV1 db 0 ifdef Support_4_IDE dw offset DGROUP:HDDE_ITEM,offset DGROUP:DRV2 db 3 dw offset DGROUP:HDDF_ITEM,offset DGROUP:DRV3 db 2 endif ;Support_4_IDE public Type_To_DrvParm_End ;R45 Type_To_DrvParm_End Label Near align 4 ;R25 public SHADOW_DR SHADOW_DR proc near ;R42ifdef Support_4_IDE ;R42 mov cx,4 ;R42else ;Support_4_IDE ;R42 mov cx,2 ;R42endif ;Support_4_IDE ;R42 start ;R45 mov ax,g_ram ;R45 mov ds,ax ;R45 mov byte ptr HDD_MODE_FLAG,0 ;R42 end mov byte ptr Post_Auto_type[bp],46 lea bx,Type_To_DrvParm Set_Parm_Loop: push bx mov bx,es:[bx] call Get_HDD_CMOS_Info pop di push di ;R45 push dx ;R42 mov al,cs:[di+4] ;get HDD type mov di,cs:[di+2] jnz short Is_User_Type mov al,[bp+si] mov ah,FIXED_TYPE[bp] cmp bx,offset DGROUP:HDDC_ITEM jne short @F shr ah,4 jmp short Get_Std_Type @@: cmp bx,offset DGROUP:HDDD_ITEM jne short Set_Std_Parm and ah,0fh Get_Std_Type: cmp ah,0fh je short Set_Std_Parm mov al,ah Set_Std_Parm: or al,al ;is type 0? jnz short @F ;No,jump mov al,15 ;set hdd type is 15 (reserve type) @@: dec al xor ah,ah shl ax,4 lea si,DGROUP:HDISK_PARMS ; si = offset into BIOS add si,ax ;R42 push cs ;R42 pop ds mov cx,16 ;R42 rep movsb ;R42 start @@: mov al,cs:[si] inc si stosb loop @B ;R42 end jmp short Set_Next_Parm Is_User_Type: xor ah,ah POST_func_call Set_HDD_parm Set_Next_Parm: ;R42 start ;R45 pop si ;R45 add si,7*ITEM_SIZE ;R45 call GetItem_Value ;R45 or HDD_MODE_FLAG,al ;R45 ror HDD_MODE_FLAG,2 ;R45 call GetItem_Cmos ;R45 mov bx,si ;R45 xor dh,dh ;R45 mov dl,al ;R45 push ds ;R45 push 0f000h ;R45 pop ds ;R45 call Write_Item_Value ;R45 pop ds ;R42 end pop bx add bx,5 cmp bx,offset Type_To_DrvParm_End ;R42 jne short Set_Parm_Loop jne Set_Parm_Loop ;R42 ;R42A start ;R45ifndef Support_4_IDE ;R45 shr HDD_MODE_FLAG,4 ;R45endif ;Support_4_IDE ;R42A end ret SHADOW_DR endp ;R06 start align 4 ;R25 public Restore_Cyrix_Reg Restore_Cyrix_Reg proc near mov bl,al ;R06A mov al,CMOS_AWARD_2 NMI_OFF ;R06A out CMOS,al ;R06A NEWIODELAY ;R06A ;R06A in al,CMOS+1 ;R06A and al,CPU_TYPE_MASK ;R06A ;R06A cmp al,TYPE_CX486S ;R06A je short Restore_Cy486 ;R06A cmp al,TYPE_CX486S2 ;R06A je short Restore_Cy486 ;R06A ;R06A cmp al,TYPE_486SLC ;R06A je short Restore_Cy486 ;R06A cmp al,TYPE_486DLC ;R06A je short Restore_Cy486 ;R06A cmp al,TYPE_M7 ;R06A jne short Not_Cy1 ;R06A ;R06ARestore_Cy486: ;R35 - start push es push ds mov ax,G_RAM mov es,ax ASSUME ES:G_RAM test byte ptr es:[SYSTEM_FLAG],Cyrix_CPU ;R54 jz short End_Job ;R54 push cs pop ds mov si,offset Cyrix_Save_Data mov cx,No_Of_Save_Data or bl,bl jnz short Restore_Data @@: lodsb out 22h,al lodsw mov di,ax in al,23h mov es:[di],al loop short @B jmp short End_Job Restore_Data: lodsb out 22h,al lodsw mov di,ax mov al,es:[di] out 23h,al loop short Restore_Data End_Job: pop ds pop es ;R35 - end ;R35 mov ax,G_RAM ;R35 mov ds,ax ;R35 ASSUME DS:G_RAM ;R35 ;R35 mov al,0C2h ;R35 out 22h,al ;R35;R06A NEWIODELAY ;R35 ;R35 or bl,bl ;save or restore ;R35 jz short @f ;save ;R35 ;R35 mov al,byte ptr ds:[Cyrix_C2_Reg] ;R35 out 23h,al ;R35;R06A NEWIODELAY ;R35 jmp short Not_Cy1 ;R35@@: ;R35 in al,23h ;R35;R06A NEWIODELAY ;R35 mov byte ptr ds:[Cyrix_C2_Reg],al ;R35 ;R35Not_Cy1: ret Restore_Cyrix_Reg endp ;R06 end ;R35 - start Cyrix_Save_Data: db 0C1h dw offset Cyrix_C1_Reg db 0C2h dw offset Cyrix_C2_Reg db 0C3h ;R38 dw offset Cyrix_C3_Reg ;R38 No_Of_Save_Data EQU ( $ - Cyrix_Save_Data ) / 3 ;R35 - end ifdef Skip_HDD_Type_1_To_46 ;R87 PUBLIC HDISK_PARMS ;R87 HDISK_PARMS LABEL WORD ;R87 else ;Skip_HDD_Type_1_To_46 ;R87 include hdtable.inc endif ;Skip_HDD_Type_1_To_46 ;R87 QUERY_SYSTEM_ADDRESS_MAP equ 1 ifdef QUERY_SYSTEM_ADDRESS_MAP public Setup_PS2 Setup_PS2: ;Set 639kb-640kb reserved as PS2 mouse buffer mov ax,G_RAM mov ds,ax assume ds:G_RAM ;R135 test byte ptr G_RAM:Hardware,00000100b ; PS/2 installed ? mov si,offset CONFIG_TABLE ;R135 test byte ptr cs:[si+5],04H ;EBDA enabled ? ;R135 jz short No_PS2_Mouse mov si,offset ExtData1Kb mov byte ptr es:[si+16],2 ;set extended data 1kb reserved No_PS2_Mouse: ;Set extended memory size ;R82 mov eax,EXT_MEM_SIZE[bp] ; get memory found (kb) ;R82 shl eax,10 ; convert to byte unit ;R82 mov si,offset ExtMem128Mb ;R82 mov es:[si+8],eax ;set extended memory size ;R82 - start call Ct_MemHole_Status ; get hole status or al,al ; 15-16Mb hole enabled ? mov eax,EXT_MEM_SIZE[bp] ; get memory found (kb) jz short Hole_Disabled ;Hole enabled , check if total 16Mb only cmp eax,15*1024 ; memory size bigger than 15Mb ifndef ACPI_Support ;R111 jbe short Mb16_Only ;R111 start else; ACPI_Support je short Mb16_Only ;ACPI jb Hole_Disabled ;ACPI endif; ACPI_Support ;R111 end sub eax,15*1024 mov si,offset MemAbove_15Mb shl eax,10 ; convert to byte unit ;R111 start ifdef ACPI_Support ;if ACPI enable, subtract total mem with ACPI tables and NVS mov si, offset ACPITableAddress mov ebx, es:[si+8] ;get length of ACPI table mov si, offset ACPINVSAddress add ebx, es:[si+8] ;add w/ length of ACPI NVS sub eax, ebx ;subtract fr total ext mem size mov si,offset MemAbove_15Mb ;R111A endif; ACPI_Support ;R111 end mov es:[si+8],eax ;set extended memory size ;R111 start ifdef ACPI_Support or ebx,ebx ;R133 jz short ACPI_OFF ;R133 ;if ACPI enable, fill in ACPITableAddress and ACPINVSAddress entries mov si, offset ACPINVSAddress add eax, 1000000h ;add total length to top 16Mb mov es:[si], eax ;fill in ACPINVSAddress mov di,offset ACPI_Memory ;R143 mov es:[di],eax ;R143 add eax, es:[si+8] ;add ACPI NVS length mov si, offset ACPITableAddress mov es:[si], eax ;fill in ACPITableAddress ACPI_OFF: ;R133 endif; ACPI_Support ;R111 end ;R143 jmp short Query_Tbl_Exit jmp Query_Tbl_Exit ;R143 Mb16_Only: mov eax,14*1024 ; set 14Mb for 16Mb size with ; hole enabled Hole_Disabled: mov si,offset ExtMem128Mb shl eax,10 ; convert to byte unit ;R111 start ifdef ACPI_Support ;if ACPI enable, subtract total mem with ACPI tables and NVS mov si, offset ACPITableAddress mov ebx, es:[si+8] ;get length of ACPI table mov si, offset ACPINVSAddress add ebx, es:[si+8] ;add w/ length of ACPI NVS test ebx, 111111111111b ;R111B jz short _No_Ass ;R111B and ebx,not 111111111111b ;R111B add ebx, 1000000000000b ;R111B _No_Ass: ;R111B sub eax, ebx ;subtract fr total ext mem size mov si,offset ExtMem128Mb endif; ACPI_Support ;R111 end mov es:[si+8],eax ;set extended memory size ;R111 start ifdef ACPI_Support or ebx,ebx ;R133 jz short ACPI_OFF1 ;R133 ;if ACPI enable, fill in ACPITableAddress and ACPINVSAddress entries mov si, offset ACPINVSAddress add eax, 100000h ;add total length to top 1Mb mov es:[si], eax ;fill in ACPINVSAddress mov di,offset ACPI_Memory ;R143 mov es:[di],eax ;R143 add eax, es:[si+8] ;add ACPI NVS length mov si, offset ACPITableAddress mov es:[si], eax ;fill-in ACPITableAddress ACPI_OFF1: ;R133 endif; ACPI_Support ;R111 end mov si,offset MemHole_15Mb mov byte ptr es:[si],-1 ;mark end of table ;R133 - start ifdef ACPI_Support or ebx,ebx jz short ACPI_OFF2 push ds push es pop ds extrn ADDR_RNG_SIZE:ABS mov cx,ADDR_RNG_SIZE shl cx,1 inc cx mov si,offset ACPITableAddress mov di,offset MemHole_15Mb rep movsb pop ds ACPI_OFF2: endif ;ACPI_Support ;R133 - end Query_Tbl_Exit: ;R82 - end ;R76 - starts ifdef PNP_BIOS extrn EXT_MEM_RESOURCE_LOC:near mov si, offset EXT_MEM_RESOURCE_LOC mov eax,EXT_MEM_SIZE[bp] ; get memory found (kb);R82 shl eax,10 ; convert to byte unit ;R82 mov es:[si+8], eax ;R116C;R116 - start ;R116Cifdef DAEWOO_5571_PATCH ;R116C;R116A extrn DirtyAddr:near ;R116C extrn AGet_CfgSpace_Dword:near ;R116C extrn T9685_Dirty:near ;R116C;R116A mov si,offset DirtyAddr ;R116C;R116A add eax,1024*1024 ;starting dirty address ;R116C;R116A mov es:[si+4], eax ;R116C ;R116C;R116B - start ;R116C ;Don't build device node if USB controller enabled to prevent ;R116C ;resource confilict ;R116C extrn Usb_Item:near ;R116C extrn GetItem_Value:near ;R116C mov si,offset USB_ITEM ;check USB controller status ;R116C call GetItem_Value ;R116C or al,al ;USB disabled ;R116C jnz short Not_T9685 ;Enabled, no device node ;R116C;R116B - end ;R116C ;R116C mov dx,1023h ;vendor ID ;R116C mov cx,9660h ;device ID ;R116C xor si,si ;first device ;R116C mov ax,0b102H ;find PCI device func. call ;R116C int 1aH ;find PCI device ;R116C jc short Not_T9685 ;R116C ;R116C mov ch,bl ;device & function number ;R116C mov cl,14H ;register 14h for mem. space ;R116C call AGet_CfgSpace_Dword ;get memory space ;R116C ;R116C or eax,10000h ;R116C mov si,offset T9685_Dirty ;R116C mov es:[si+4], eax ;address ;R116C mov dword ptr es:[si+8],1000h ;size ;R116C mov dword ptr es:[si-4],20000h ;size ;R116CNot_T9685: ;R116Cendif; DAEWOO_5571_PATCH ;R116C;R116 - end endif ;PNP_BIOS ;R76 - ends ret endif; QUERY_SYSTEM_ADDRESS_MAP ;R27 - start ;R135 public Disable_PS2_Mouse_Flag ;R135Disable_PS2_Mouse_Flag: ;R135;R27A - start ;R135 push es ;R135 mov ah,0c0h ;R135 int 15h ;Get system config. in es:bx ;R135 mov si,bx ;R135 pop es ;R135 and byte ptr es:[si+5],NOT 04H ;R135;R27A - end ;R135 ;R135;R27A and byte ptr es:[CONFIG_TABLE+5],NOT 04H ;disable mouse flag ;R135 ret ;R135;R27 - end ;R135 ;R36 - start ifdef MP_SUPPORT ;R114;[]==============================================================[] ;R114; ;R114; Cpu2_Init: ;R114; ;R114; Detect second CPU and initial APIC ;R114; ;R114;Saves: ;R114; ;R114; All except ax,dx,es,ds,flag ;R114;Input : None ;R114;Output: None ;R114; ;R114;[Notes] ;R114; ;R114;[]==============================================================[] ;R114 ;R114CPU2_Init proc near ;R114;R48 - start ;R114ifdef P6_BIOS_ONLY ;R114;Code for P6 ;R114 cli ;R114NotVacant EQU 0ffh ;R114Vacant EQU 00h ;R114 ;R114 mov byte ptr es:[050AH],-1h ;R109A Set Init Start Flag ;R114 mov al, NotVacant ;R114 xor bx,bx ;R114 mov es,bx ;R114 ;R114TestLock: ;R114 xchg byte ptr es:[0501H],al ;Lock semaphore ;R114 cmp al,NotVacant ;Someone in critical section? ;R114 jz short TestLock ;Yes, check semaphore again ;R114 ;R114; add byte ptr es:[0500H],1 ;CPU count increment ;R114 mov byte ptr es:[500H],0AAH ;Kludge! work for dual processors only ;R114ReleaseLock: ;R114 mov al,Vacant ;Release the lock ;R114 xchg byte ptr es:[0501H],al ;Release the lock ;R114 ;R114;R105;R70 - start ;R114;R105 mov eax,2 ;read cache isze ;R114;R105 db 0Fh,0A2h ;OP code: CPUID ;R114;R105 mov es:[0502H],dl ;save L2 cache size ;R114;R105;R70 - end ;R114 ;R114;R74 - start ;R114 mov eax,1 ;read CPUID ;R114 db 0Fh,0A2h ;OP code: CPUID ;R114 mov es:[0504H],eax ;save 2nd's CPUID ;R114;R74 - end ;R114 ;R114;R51 - start ;R114 ;set up stack for far call operation ;R114 mov ax,cs ;R114 mov ss,ax ;R114 mov sp,2000H ;R114 ;R114 ;Set MTRR register for second CPU ;R114 FAR_CALL ,0E000H ;set MTRR registers ;R114;R51 - end ;R114 ;R114;R104 - starts ;R114 mov si, 508h ;R114 call Read_P6_Update_Version ;R114;R104 - ends ;R114 ;R114;R105 - start ;R114;Read L2 cache size and store in temporary area ;R114 xor ax,ax ;R114 mov es,ax ;setup segment ;R114 mov eax,2 ;read cache isze ;R114 db 0Fh,0A2h ;OP code: CPUID ;R114 mov es:[0502H],dl ;save L2 cache size ;R114;R105 - end ;R114 ;R114;R85 hlt ;R114 mov byte ptr es:[050AH],5Ah ;R109 Set Init End Flag ;R114 FAR_JMP , 0F000h ;R85 ;R114 ;R114else; P6_BIOS_ONLY ;R114;Code for P5 ;R114 cli ;R114 xor ax,ax ;R114 mov es,ax ;R114 mov byte ptr es:[0500H],0AAH ;set CPU detected ;R114;R84 hlt ;R114 far_jmp , 0F000h ;R84 ;R114endif; P6_BIOS_ONLY ;R114;R48 - end ;R114 ;R114;R104 - starts ;R114Read_P6_Update_Version Proc Near ;R114 ;R114 pushad ;R114 ;R114 mov ecx, 8Bh ;R114 xor eax, eax ;R114 xor edx, edx ;R114 WRMSR ;R114 ;R114 mov eax, 1 ;R114 db 0Fh, 0A2h ;R114 ;R114 mov ecx, 8Bh ;R114 RDMSR ;R114 ;R114 mov es:[si], dl ;save 2nd CPUID version ;R114 ;R114 popad ;R114 ret ;R114 ;R114Read_P6_Update_Version Endp ;R114;R104 - ends ;R114 ;R114CPU2_Init_Len EQU $-offset CPU2_Init ;R114CPU2_Init endp ;R47 GDTR1: ; global descriptor table register ;R47 dw 8*3 ; LIMIT ;R47 dw offset GDT1 ;R47 dw 0fh ; in 0F000h segment ;R47 ;R47GDT1: ; null descriptor ;R47 dw 0 ; limit ;R47 dw 0 ; base ;R47 db 0 ; hibase ;R47 db 0 ; access ;R47 db 0 ; hilimit ;R47 db 0 ; msbase ;R47 ;R47CODE1_DT: ; cs - prom code segment ;R47CODE1_INDEX = ((offset CODE1_DT - offset GDT1)/8) SHL 3 ;R47 ;R47 dw 0ffffh ; limit ;R47 dw 0 ; base a15-a0 ;R47 db 0fh ; hibase a23-a16, assume we have 64k prom ;R47 db 9fh ; access ;R47 db 0 ; hilimit ;R47 db 0 ; msbase a31-a24 ;R47 ;R47DATA1_DT: ; ds - first 64k segment ;R47DATA1_INDEX = ((OFFSET DATA1_DT - OFFSET GDT1)/8) SHL 3 ;R47 dw 0ffffh ; limit ;R47 dw 0 ; base data segment points to ;R47 db 0 ; hibase ; 00000000 ;R47 db 93h ; access ;R47 db 08fh ; hilimit (4GB) ;R47 db 0 ; msbase Enter_Prot_mode: mov ax,cs mov ds,ax assume ds:dgroup mov si, offset GDTR1 lgdt fword ptr ds:[si] ;load descriptor table mov eax,cr0 ;Enter protected mode or al,1 mov cr0,eax jmp short Enter_Protect_Mode1 ALIGN 16 Enter_Protect_Mode1: mov ax,DATA1_INDEX mov ds,ax ; ds = 00000000h ret Back_Real_Mode: mov eax, cr0 and al, not 1 mov cr0, eax FAR_JMP $+4, 0f000h ret endif; MP_SUPPORT ;R114 public Init_APIC ;R114Init_Apic proc near ;R114ifdef MP_SUPPORT ;R114 ;R114;R48 - start ;R114ifdef P6_BIOS_ONLY ;R114;Code for P6 ;R114 push ds ;R114 push es ;R114 push esi ;R114 ;R114 push ds ;R114 xor ax, ax ;R114 mov ds, ax ;R114 mov ds:byte ptr [500H], 0 ;R114 mov ds:byte ptr [501H], Vacant ;R114 pop ds ;R114 ;R114;R62 - start ;R114;Check if IO APIC exist or not, if not , disable P6 local APIC and ;R114;skip initialization ;R114 call Enter_Prot_mode ;R114 mov esi,0FEC00000H ;I/O APIC address ;R114 xor eax,eax ;test pattern ;R114 mov [esi],eax ;write APIC reg. addr. ;R114 mov ecx,[esi] ;Read APIC reg. addr. ;R114 cmp al,cl ;I/O APIC existed ? ;R114 pushf ;R114 call Back_Real_Mode ;R114 popf ;R114 je short IO_Apic_Exist ;R114 ;R114;disable local APIC if not support MP ;R114 mov ecx,27 ;MSR index 27 ;R114 RDMSR ;R114 and ah,NOT 08H ;disable CPU APIC ;R114 WRMSR ;R114 ;R114;R64 jmp short No_IO_Apic ;R114 jmp No_IO_Apic ;R64 ;R114 ;R114IO_Apic_Exist: ;R114;R62 - end ;R114 ;R114 ;R114 call Cpu_Apic_Init ;R114 ;R114 call Enter_Prot_mode ;R114 ;R114;R85 - start ;R114 ;**** Set I/O APIC ID ;R114 mov esi, 0fec00000h ;R114 mov eax, ds:dword ptr [esi] ;R114 xor al,al ; set index 0 ;R114 mov ds:dword ptr [esi], eax ; index ;R114 ;R114 mov eax, ds:dword ptr [esi+10h] ;R114 and eax, 0f0ffffffh ;R114 or eax, 002000000h ; set ID to 2 ;R114 mov ds:dword ptr [esi+10h], eax ; index ;R114 ;R114 ;set Local APIC ID to 0 for BSP CPU ;R114 mov esi,0fee00020h ;local APIC ID ;R114 xor eax,eax ;set ID to 0 ;R114 mov [esi],eax ;R114 ;R114;R85 - end ;R114 ;R114 ;*** Send Startup IPI to Detect if CPU2 Present ;R114 mov esi, 000f0000h ;R114 mov si, offset CPU2_Init ;R114 mov cx, CPU2_Init_Len ;R114;R108 mov edi, 00040000h ;R114 mov edi, CPU2_SEGMENT shl 4 ;R108 ;R114 @@: ;R114 mov al, ds:byte ptr [esi] ;R114 mov ds:byte ptr [edi], al ;R114 inc di ;R114 inc si ;R114 loop short @B ;R114 ;R114 mov byte ptr es:[050AH],5Ah ;R109A Set CPU2 init end Flag ;R114 ;R114 ;*** Clear ESR first ;R114 mov esi, 0fee00280h ; ESR ;R114 xor eax, eax ;R114 mov ds:dword ptr [esi], eax ;R114 mov eax, ds:dword ptr [esi] ;R114 ;R114 ;*** Set ICR Low ;R114 mov si, 0300h ; ICR Low ;R114 mov eax, ds:dword ptr [esi] ;R114 and eax, 0ffff3800h ;R114;R108 or eax, 0000CC640h ; 4000:0 ;R114 or eax, 0000CC600h + (CPU2_SEGMENT shr 8) ;R108 ;R114 mov [esi], eax ;R114 ;R114 ;*** Loop for Some Time ; R109A ;R114 mov cx, 1000h ; R109A ;R114 @@: ; R109A ;R114 NEWIODELAY ; R109A ;R114 loop short @B ; R109A ;R114 NANANA: ; R109 ;R114 cmp byte ptr es:[050AH],5Ah ; R109 Wait CPU2 Init ;R114 jne short NANANA ; R109 ;R114;R109 ;*** Loop for Some Time ;R114;R109 mov cx, 1000h ;R114;R109 @@: ;R114;R109 NEWIODELAY ;R114;R109 loop short @B ;R114 ;R114;R49 - start ;R114;record CPU APIC ID and version and save it in MP table ;R114 mov eax,dword ptr ds:[0fee00020h] ;local APIC ID in BL ;R114 shr eax,24 ;R114 and al,0fH ;legal value 0..F ;R114 mov bl,al ;R114 ;R114 mov eax,dword ptr ds:[0fee00030h] ;local APIC version in BH ;R114 mov bh,al ;R114;R49 - end ;R114 ;R114 call Back_Real_Mode ;R114 ;R114;R64 call CheckSum_Mp_Table ;R114 ;R114;R64 - start ;R114 ;R114;First - Force system BIOS readable and shadow RAM writeable ;R114 extrn F000_Shadow_W:near ;R114 push bx ;save APIC ID ;R64A ;R114 call F000_Shadow_W ;R114;R64A - start ;R114 ;Read CPU ID and save in MP table ;R114 mov eax,1 ;eax = 1 to read CPU ID ;R114 db 0fh,0A2h ;CPU ID instruction ;R114 mov dword ptr cs:[P1_SiGn],eax ;save CPU signature for CPU 1 ;R114 ;R114 mov dword ptr cs:[P2_SiGn],eax ;save CPU signature for CPU 1 ;R114;R74 - start ;R114 xor ax,ax ;R114 mov es,ax ;temporary segment ;R114 cmp byte ptr es:[500H],0AAH ;2 CPUs plugged ;R114 jne short No_2ndCpu ;R114 ;R114 mov eax,dword ptr es:[0504H] ;get 2nd CPUID ;R114 mov dword ptr cs:[P2_SiGn],eax ;save CPU signature for CPU 2 ;R114 ;R114;R104 - starts ;R114 ;save 2nd CPU's update version ;R114 mov al, byte ptr es:[0508H] ;R114 mov byte ptr cs:[P2_Upd_Ver], al ;R114;R104 - ends ;R114 ;R114No_2ndCpu: ;R114;R74 - end ;R114 ;R114;R104 - starts ;R114 ;save 1st CPU's update version ;R114 mov si, 508h ;R114 call Read_P6_Update_Version ;R114 mov al, es:[si] ;R114 mov cs:[P1_Upd_Ver], al ;R114;R104 - ends ;R114 ;R114;R64A - end ;R114 pop bx ;restore APIC ID ;R64A ;R114 ;R114 mov si,offset Process_Entry1 ;R114 mov cs:[si+1],bx ;save local APIC ID and version ;R114 mov si,offset Process_Entry2 ;R114 xor bl,01H ;exclusive ID for second CPU ;R114 mov cs:[si+1],bx ;save local APIC ID and version ;R114 ;R114;Last - Force system BIOS shadow RAM readonly ;R114 extrn F000_Shadow_R:near ;R114 call F000_Shadow_R ;R114;R64 - end ;R114 ;R114 call Temp_SMBase_For_2nd_CPU ;R89 ;R114 ;R114No_IO_Apic: ;R62 ;R114 ;R114 pop esi ;R114 pop es ;R114 pop ds ;R114else; P6_BIOS_ONLY ;R114;Code for P5 ;R114 ;R114 push ds ;R114 push es ;R114 push esi ;R114 ;R114 call Cpu_Apic_Init ;R114 ;R114;R84A call Temp_SMBase_For_2nd_CPU ;R84 ;R114 ;R114 call Enter_Prot_mode ;R114 ;R114 ;**** Set I/O APIC ID ;R114 mov esi, 0fec00000h ;R114 mov eax, ds:dword ptr [esi] ;R114 mov al, 00h ;R114 mov ds:dword ptr [esi], eax ; index ;R114 ;R114 mov eax, ds:dword ptr [esi+10h] ;R114 and eax, 0f0ffffffh ;R114 or eax, 002000000h ; set ID to 2 ;R114 mov ds:dword ptr [esi+10h], eax ; index ;R114 ;R114 ;R114 ;*** Set ICR High ;R114 mov esi, 0fee00310h ; ICR High ;R114 mov eax, ds:dword ptr [esi] ;R114 and eax, 0f0ffffffh ;R114 or eax, 001000000h ; ID ;R114 mov [esi], eax ;R114 ;*** Set ICR Low ;R114 mov si, 0300h ; ICR Low ;R114 mov eax, ds:dword ptr [esi] ;R114 and eax, 0fffff8ffh ;R114 or ax, 0c500h ; Assert Init ;R114 mov [esi], eax ;R114 mov cx, 1000h ;R114 @@: ;R114 NEWIODELAY ;R114 loop short @B ;R114 ;R114 ;R114 ;*** Send Startup IPI to Detect if CPU2 Present ;R114 mov esi, 000f0000h ;R114 mov si, offset CPU2_Init ;R114 mov cx, CPU2_Init_Len ;R114;R108 mov edi, 00040000h ;R114 mov edi, CPU2_SEGMENT shl 4 ;R108 ;R114 @@: ;R114 mov al, ds:byte ptr [esi] ;R114 mov ds:byte ptr [edi], al ;R114 inc di ;R114 inc si ;R114 loop short @B ;R114 ;R114 mov cx, 10 ;R114Startup_IPI_Loop: ;R114 push cx ;R114 ;*** Clear ESR first ;R114 mov esi, 0fee00280h ; ESR ;R114 xor eax, eax ;R114 mov ds:dword ptr [esi], eax ;R114 mov eax, ds:dword ptr [esi] ;R114 ;R114 ;*** Set ICR High ;R114 mov si, 0310h ; ICR High ;R114 mov eax, ds:dword ptr [esi] ;R114 and eax, 0f0ffffffh ;R114 or eax, 001000000h ;R114 mov [esi], eax ;R114 ;*** Set ICR Low ;R114 mov si, 0300h ; ICR Low ;R114 mov eax, ds:dword ptr [esi] ;R114 and eax, 0ffff3800h ;R114;R108 or ax, 0640h ; 4000:0 ;R114 or ax, 0600h + (CPU2_SEGMENT shr 8) ;R108 ;R114 mov [esi], eax ;R114 ;*** Loop for Some Time ;R114 mov cx, 1000h ;R114 @@: ;R114 NEWIODELAY ;R114 loop short @B ;R114 pop cx ;R114 loop short Startup_IPI_Loop ;R114 ;R114;R49A ;R49 - start ;R114;R49A ;record CPU APIC ID and version and save it in MP table ;R114;R49A mov eax,[0fee00020h] ;local APIC ID in BL ;R114;R49A mov bl,al ;R114;R49A ;R114;R49A mov eax,[0fee00030h] ;local APIC version in BH ;R114;R49A mov bh,al ;R114;R49A ;R49 - end ;R114 ;R114 call Back_Real_Mode ;R114 ;R114 call Temp_SMBase_For_2nd_CPU ;R84A ;R114 ;R114;R64 call CheckSum_Mp_Table ;R114 ;R114 pop esi ;R114 pop es ;R114 pop ds ;R114endif; P6_BIOS_ONLY ;R114;R48 - end ;R114endif; MP_SUPPORT ;R114 ret ;R114Init_Apic endp ;R64 ifdef MP_SUPPORT ;R64 ;R59 extrn MP_FP_CHKSUM:ABS ;R64 ;R59 extrn MP_FP_LENGTH:ABS ;R64 ;R59 extrn MP_FP_Stru:near ;R64 ;R59 extrn MP_Config_Table:near ;R64 ;R59 extrn MPCFG_LEN:ABS ;R64 ;R59 extrn MP_CFG_CHKSUM:ABS ;R64 ;Input : BL - Local APIC ID number of BSP ;R49 ;R64 ; BH - Local APIC version number ;R49 ;R64 ;Output: None ;R49 ;R64 CheckSum_Mp_Table proc near ;R64 ;Build MP table and re-calculate checksum ;R64 ;Second - calculate checksum of MP Floating Pointer structure ;R64 push cs ;R64 pop ds ;DS point to FP structure ;R64 ;R64 ;First - Force system BIOS readable and shadow RAM writeable ;R64 extrn F000_Shadow_W:near ;R64 call F000_Shadow_W ;R64 ;R64 ;R49 - start ;R64 ifdef P6_BIOS_ONLY ;R49A ;R64 ;R59 extrn Process_Entry1:near ;R64 ;R59 extrn Process_Entry2:near ;R64 mov si,offset Process_Entry1 ;R64 mov [si+1],bx ;save local APIC ID and version ;R64 mov si,offset Process_Entry2 ;R64 xor bl,01H ;exclusive ID for second CPU ;R64 mov [si+1],bx ;save local APIC ID and version ;R64 endif; P6_BIOS_ONLY ;R49A ;R64 ;R49 - end ;R64 ;R64 mov si,offset MP_FP_Stru ;checksum stating location ;R64 mov cx,MP_FP_LENGTH ;length to check sum ;R64 xor bl,bl ;initial checksum ;R64 cld ;R64 Check_Sum1: ;R64 lodsb ;R64 add bl,al ;R64 loop short Check_Sum1 ;R64 ;R64 neg bl ;checksum byte ;R64 mov si,MP_FP_CHKSUM ;R64 add si,offset MP_FP_Stru ;R64 mov [si],bl ;R64 ;R64 ;Third - calculate checksum of MP Configuration Table ;R64 mov si,offset MP_Config_Table;checksum stating location ;R64 mov cx,MPCFG_LEN ;length to check sum ;R64 xor bl,bl ;initial checksum ;R64 cld ;R64 Check_Sum2: ;R64 lodsb ;R64 add bl,al ;R64 loop short Check_Sum2 ;R64 ;R64 neg bl ;checksum byte ;R64 ;R64 ;R64 mov si,MP_CFG_CHKSUM ;R64 add si,offset MP_Config_Table ;R64 mov [si],bl ;R64 ;R64 ;R64 ;Last - Force system BIOS shadow RAM readonly ;R64 extrn F000_Shadow_R:near ;R64 call F000_Shadow_R ;R64 ;R64 ret ;R64 CheckSum_Mp_Table endp ;R64 ;R64 CPUMsg db ', 1',0 ;R64 CpuMsgCommon db ' Processor(s) Detected',0 ;R64 CPUMsg1 db ', 2',0 ;R64 endif; MP_SUPPORT ;R64 ;R64 public Show_Processor_Number ;R64 Show_Processor_Number Proc Near ;R64 ifdef MP_SUPPORT ;R64 push cs ;R64 pop ds ;DS point to FP structure ;R64 ;*** Display CPU 2 String ;R64 mov si, offset CPUMsg ;R64 xor ax,ax ;R64 mov es,ax ;R64 cmp byte ptr es:[0500H],0aaH ;R64 jne short @F ;R64 mov si, offset CPUMsg1 ;2 CPU detected ;R64 @@: ;R64 extrn Display_String:Near ;R64 call Display_String ;R64 ;R64 mov si, offset CPUMsgCommon ;R64 call Display_String ;R64 endif; MP_SUPPORT ;R64 ret ;R64 Show_Processor_Number ENDP public Cpu_Apic_Init Cpu_Apic_Init proc near ifdef MP_SUPPORT ;;Program local APIC for dual processor operation ;;1. Set error vector to 7fh ;;2. Enable the APIC by setting the Unit Enable bit in the spurious vector ;; register, and set vector to 0fh ;;3. Setup Local Int0 vector table(unmasked,edge,active high, ;; Delivery Mode = ExtInt) ;;4. Setup Local Int1 vector table(unmasked,edge,active high, ;; Delivery Mode = NMI) ERROR_VECT EQU 0FEE00370H SPUR_VECT EQU 0FEE000F0H LINT0_VECT EQU 0FEE00350H LINT1_VECT EQU 0FEE00360H ;Save Interrupt mask and disable all interrupt in al,0a1H ;read secondary IMR mov ah,al mov al,0ffh out 0a1H,al in al,021H ;read primary IMR push ax mov al,0ffh out 021H,al call Enter_Prot_mode ;Initial I/O APIC , otherwise SCO/UNIX can not recognize second CPU ;when system shutdown and reboot IO_APIC_unit EQU 0fec00000h mov esi,IO_APIC_unit mov edi,10h xor ebx,ebx IO_init_loop: mov edx,1 mov [esi],edx mov [esi+10h],ebx mov [esi],edx mov ecx,[esi+10h] mov [esi],edx mov eax,0ffffffffh mov [esi+10h],eax mov dword ptr [esi],edx mov eax,[esi+10h] and eax,0ff0000h and ecx,0ff0000h cmp eax,ecx jne short Next_IO_Addr shr eax,10h cmp ax,0efh jg short Next_IO_Addr shr ecx,10h cmp cx,0efh jg short Next_IO_Addr mov ecx,78h mov [esi],ebx mov [esi+10h],ebx mov eax,0fh mov edx,10000h @@: inc eax mov [esi],eax mov [esi+10h],edx inc eax mov [esi],eax mov [esi+10h],ebx loop short @B mov dword ptr [esi],ebx Next_IO_Addr: add esi,1000h dec edi jnz IO_init_loop ;2. Enable APIC and set vector to 0FH ;** The APIC spurious interrupt must be pointed to a vector ;** whose lower nybble is 0f, that is 0xf, where x is 0-f. ;** Here we use int 00fH, which handles spurious interrupts and ;** supplies the necessary IRET. ;** This vector is assumed to have already been initiailized in memory ;** Enable the APIC via SVR, and set the spurious interrupt to use ;** Int 00f mov esi, SPUR_VECT ; point to spurious vector loc. mov eax,[esi] and eax,0FFFFFF0FH ;set vector to 0fh or ah,01h ; set UNIT enable mov [esi],eax ;3. Setup local Int0 vector ;** Program LVT1 as ExtInt which delivers the signal to the ;** INTR signal of all processor's cores listed in the ;** destination as an interrupt that originated in an ;** externally connected interrupt controller. mov esi, LINT0_VECT ; point to LINT 0 vector loc. mov eax,[esi] ;R58 and eax,0FFFE58FFH ;R58 or ah,07h ; Extint and eax,0FFFE00FFH ;R58 or ah,57h ; Extint ;R58 mov [esi],eax ;4. Setup local Int1 vector ;** Program LVT2 as NMI which delivers the signal on the NMI ;** signal of all processor's cores listed in the destination. mov esi, LINT1_VECT ; point to LINT 1 vector loc. mov eax,[esi] ;R58 and eax,0FFFE58FFH ;R58 or eax,0FFFF0400h ; delivery mode = NMI and eax,0FFFE00FFH ;R58 or ah,54h ; NMI ;R58 mov [esi],eax call Back_Real_Mode ;restore Interrupt mask pop ax out 021h,al ;restore primary IMR xchg ah,al out 0a1h,al ;restore secondary IMR endif; MP_SUPPORT ret Cpu_Apic_Init endp ;R36 end ;R59 - start ifdef MP_SUPPORT ;R114 ;R114;R84 - starts ;R114;Function : Deliver a SMI to 2nd CPU for changing SMBASE to avoid SMBASE ;R114; conflict with 1st CPU while changing 1st CPU's SMBase by issue ;R114; software SMI by chipset. ;R114;Note : This routine should invoked before 1st CPU's SMI be initiated ;R114;Input : none ;R114;Output : none ;R114 Public Temp_SMBase_For_2nd_CPU ;R114Temp_SMBase_For_2nd_CPU Proc Near ;R114 ;R114;R103 - starts ;R114 Post_Func_Call If_MP_PLUGGED ;R114 jnc short @F ;R114 ret ;R114 @@: ;R114;R103 - ends ;R114 ;R114 ;R114 ;Copy change SMBASE code into original SMBASE 3800:0 for SMBase ;R114 ;changing. ;R114 mov ax,cs ;R114 mov ds,ax ; source address ;R114 mov ax,03800h ; orginal CPU SMBase ;R114 mov es,ax ; destination address ;R114 mov cx,8000h ;R114 mov si,offset @F ; code for change SMBASE ;R114 xor di,di ;R114 cld ;R114 rep movsb ;R114 ;R114 call Enter_Prot_mode ;R114 ;R114 ;Deliver a SMI to 2nd CPU to change SMBASE by local APIC ;R114 mov esi, 0FEE00300h ; command register ;R114 mov eax, 0000C0200h ; issue SMI ;R114 mov [esi], eax ;R114 ;R114 call Back_Real_Mode ;R114 ;R114 ret ;R114 ;R114 @@: ;R114;R108 mov eax,028000h ; new SMBASE address ;R114 mov eax, (CPU2_SEGMENT shl 4) ;R108 ;R114 mov di,0FEF8h ; SMBASE register ;R114 mov dword ptr cs:[di], eax ;R114 db 0Fh, 0AAh ;RSM ;R114 ;R114Temp_SMBase_For_2nd_CPU Endp ;R114;R84 - ends align 16 ;R21A start public MP_FP_CHKSUM public MP_FP_LENGTH public MP_FP_Stru ;R114 public MP_Config_Table ;R114 public MPCFG_LEN ;R114 public MP_CFG_CHKSUM ;R114 ;R114ISA_BUS_ID EQU 1 ;R86 ;R114PCI_BUS_ID EQU 0 ;R86 ;R114 ;R21A end MP_FP_CHKSUM EQU 10 MP_FP_LENGTH EQU 16 ;length of FP structure MP_FP_VER EQU 01H ;length of FP structure MP_FP_Stru: db '_MP_' ;signature dw MP_ShadowTbl_Address ;R114 ;R114 dw offset MP_Config_Table ;address of MP config. table ;low word dw 000fH ;address of MP config. table ;high word db MP_FP_LENGTH/16 ;length, 1 paragraph(16byte) db MP_FP_VER ;version number db 00h ;check sum byte db 00h ;MP inform byte 1, 0 means ; MP config. table is present db 00h ;MP inform byte 2, bit 7 = 0 ; means virtual wire mode db 3 dup (0) ;MP inform byte 3-5, reserved dd 0 ;dummy ;R114MP_CFG_CHKSUM EQU 07H ;R114MP_Config_Table: ;R114 db 'PCMP' ;signature of MP table ;R114 dw MPCFG_LEN ;total length of MP table ;R114 db 01h ;version of MP specification ;R114 db 00h ;check sum ;R114 db 'OEM00000' ;OEM string ;R114 db 'PROD00000000' ;product family ;R114 dw 0 ;OEM table pointer addr. low ;R114 dw 0 ;OEM table pointer addr. high ;R114 dw 0 ;OEM table size ;R114 dw TOTAL_TABLE_ENTRY ;entry count ;R114 dd 0fee00000h ;local APIC address ;R114 dd 0 ;reserved ;R114 ;R114PROC_TYPE EQU 00H ;R114;R29A LOCAL_APIC_ID1 EQU 00H ;R114LOCAL_APIC_VER1 EQU 11H ;R114CPU_FLAG1 EQU 03H ;R114ifdef P6_BIOS_ONLY ;R29 ;R114;R85 LOCAL_APIC_ID1 EQU 01H ;R29A ;R114LOCAL_APIC_ID1 EQU 00H ;R85 ;R114CPU_SIGNATURE1 EQU 00000611H ;for P6 ;R29 ;R114FEATURE_FLAGS1 EQU 0000fbffH ;R29 ;R114else; P6_BIOS_ONLY ;R29 ;R114LOCAL_APIC_ID1 EQU 00H ;R29A ;R114CPU_SIGNATURE1 EQU 00000521H ;R114FEATURE_FLAGS1 EQU 000007bfH ;R114endif; P6_BIOS_ONLY ;R29 ;R114 ;R114TOTAL_ENTRY = 0 ;R114 public Process_Entry1 ;R30 ;R114 public Process_Entry2 ;R30 ;R114Process_Entry1: ;R114 db PROC_TYPE ;process entry ;R114 db LOCAL_APIC_ID1 ;local APIC ID number ;R114 db LOCAL_APIC_VER1 ;local APIC ID version ;R114 db CPU_FLAG1 ;CPU flag ;R114 public P1_SiGn ;R74 ;R114P1_SiGn: ;R64A ;R114 dd CPU_SIGNATURE1 ;CPU signature ;R114 dd FEATURE_FLAGS1 ; ;R114 dd 0 ;reserved ;R114 dd 0 ;reserved ;R114TOTAL_ENTRY = TOTAL_ENTRY + 1 ;R114 ;R114;R29A LOCAL_APIC_ID2 EQU 01H ;R114LOCAL_APIC_VER2 EQU 11H ;R114CPU_FLAG2 EQU 01H ;R114ifdef P6_BIOS_ONLY ;R29 ;R114;R85 LOCAL_APIC_ID2 EQU 00H ;R29A ;R114LOCAL_APIC_ID2 EQU 01H ;R85 ;R114CPU_SIGNATURE2 EQU 00000611H ;for P6 ;R29 ;R114FEATURE_FLAGS2 EQU 0000fbffH ;R29 ;R114else; P6_BIOS_ONLY ;R29 ;R114LOCAL_APIC_ID2 EQU 01H ;R29A ;R114CPU_SIGNATURE2 EQU 00000521H ;R114FEATURE_FLAGS2 EQU 000007bfH ;R114endif; P6_BIOS_ONLY ;R29 ;R114Process_Entry2: ;R114 db PROC_TYPE ;process entry ;R114 db LOCAL_APIC_ID2 ;local APIC ID number ;R114 db LOCAL_APIC_VER2 ;local APIC ID version ;R114 db CPU_FLAG2 ;CPU flag ;R114 public P2_SiGn ;R74 ;R114P2_SiGn: ;R64A ;R114 dd CPU_SIGNATURE2 ;CPU signature ;R114 dd FEATURE_FLAGS2 ; ;R114 dd 0 ;reserved ;R114 dd 0 ;reserved ;R114TOTAL_ENTRY = TOTAL_ENTRY + 1 ;R114 ;R114BUS_ENTRY_ID EQU 01H ;R114Bus_Entry1: ;R114 db BUS_ENTRY_ID ;bus entry ID ;R114;R86 db 00H ;bus ID ;R114;R86 if BUS_TYPE EQ EISA_BUS ;R114;R86 db 'EISA ' ;bus type string ;R114;R86 else ;BUS_TYPE EQ EISA_BUS ;R114;R86 db 'ISA ' ;bus type string ;R114;R86 endif ;BUS_TYPE EQ EISA_BUS ;R114 db PCI_BUS_ID ;R86 ;R114 db 'PCI ' ;bus type string ;R86 ;R114TOTAL_ENTRY = TOTAL_ENTRY + 1 ;R114 ;R114Bus_Entry2: ;R114 db BUS_ENTRY_ID ;bus entry ID ;R114;R86 db 01H ;bus ID ;R114;R86 db 'PCI ' ;bus type string ;R114 db ISA_BUS_ID ;R86 ;R114if BUS_TYPE EQ EISA_BUS ;R86 ;R114 db 'EISA ' ;bus type string ;R86 ;R114else ;BUS_TYPE EQ EISA_BUS ;R86 ;R114 db 'ISA ' ;bus type string ;R86 ;R114endif ;BUS_TYPE EQ EISA_BUS ;R86 ;R114TOTAL_ENTRY = TOTAL_ENTRY + 1 ;R114 ;R114IO_APIC_ID EQU 02H ;R114APIC_ENTRY_ID EQU 02H ;R114IO_Apic_Entry: ;R114 db APIC_ENTRY_ID ;I/O APIC ID ;R114 db IO_APIC_ID ;I/O apic id ;R114 db 11H ;I/O apic version ;R114 db 01H ;I/O apic flag ;R114 dd 0fec00000h ;I/O apic address ;R114TOTAL_ENTRY = TOTAL_ENTRY + 1 ;R114 ;R114IOInt_Entry_ID EQU 03H ;R114TYPE_INT EQU 0 ;R114TYPE_NMI EQU 1 ;R114TYPE_SMI EQU 2 ;R114TYPE_EXTINT EQU 3 ;R114 ;R114;IO_Int_Entry0: ;R114; db IOInt_Entry_ID ;I/O interrupt entry ID ;R114; db TYPE_EXTINT ;I/O interrupt type ;R114; dw 0005H ;active high & edge trigger ;R114; db 0 ;source bus ID ;R114; db 0 ;source bus IRQ ;R114; db 0 ;destination I/O APIC ID ;R114; db 0 ;destination I/O APIC INTIN# ;R114;TOTAL_ENTRY = TOTAL_ENTRY + 1 ;R114 ;R114;R64 - start ;R114ifdef NEW_INTEL_IOAPIC ;R114IO_Int_Entry0: ;R114 db IOInt_Entry_ID ;I/O interrupt entry ID ;R114 db TYPE_EXTINT ;I/O interrupt type ;R114 dw 0000H ;active high & edge trigger ;R114;R86 db 0 ;source bus ID ;R114 db ISA_BUS_ID ;R86 ;R114 db 0 ;source bus IRQ ;R114 db IO_APIC_ID ;destination I/O APIC ID ;R114 db 0 ;destination I/O APIC INTIN# ;R114TOTAL_ENTRY = TOTAL_ENTRY + 1 ;R114endif; NEW_INTEL_IOAPIC ;R114;R64 - end ;R114 ;R114IO_Int_Entry1: ;R114 db IOInt_Entry_ID ;I/O interrupt entry ID ;R114 db TYPE_INT ;I/O interrupt type ;R114 dw 0000H ;active high & edge trigger ;R114;R86 db 0 ;source bus ID ;R114 db ISA_BUS_ID ;R86 ;R114 db 1 ;source bus IRQ ;R114 db IO_APIC_ID ;I/O apic id ;R114 db 1 ;destination I/O APIC INTIN# ;R114TOTAL_ENTRY = TOTAL_ENTRY + 1 ;R114 ;R114IO_Int_Entry2: ;R114 db IOInt_Entry_ID ;I/O interrupt entry ID ;R114 db TYPE_INT ;I/O interrupt type ;R114 dw 0000H ;active high & edge trigger ;R114;R86 db 0 ;source bus ID ;R114 db ISA_BUS_ID ;R86 ;R114 db 0 ;source bus IRQ ;R114 db IO_APIC_ID ;I/O apic id ;R114 db 2 ;destination I/O APIC INTIN# ;R114 ;R114TOTAL_ENTRY = TOTAL_ENTRY + 1 ;R114 ;R114IO_Int_Entry3: ;R114 db IOInt_Entry_ID ;I/O interrupt entry ID ;R114 db TYPE_INT ;I/O interrupt type ;R114 dw 0000H ;active high & edge trigger ;R114;R86 db 0 ;source bus ID ;R114 db ISA_BUS_ID ;R86 ;R114 db 3 ;source bus IRQ ;R114 db IO_APIC_ID ;I/O apic id ;R114 db 3 ;destination I/O APIC INTIN# ;R114TOTAL_ENTRY = TOTAL_ENTRY + 1 ;R114IO_Int_Entry4: ;R114 db IOInt_Entry_ID ;I/O interrupt entry ID ;R114 db TYPE_INT ;I/O interrupt type ;R114 dw 0000H ;active high & edge trigger ;R114;R86 db 0 ;source bus ID ;R114 db ISA_BUS_ID ;R86 ;R114 db 4 ;source bus IRQ ;R114 db IO_APIC_ID ;I/O apic id ;R114 db 4 ;destination I/O APIC INTIN# ;R114TOTAL_ENTRY = TOTAL_ENTRY + 1 ;R114IO_Int_Entry5: ;R114 db IOInt_Entry_ID ;I/O interrupt entry ID ;R114 db TYPE_INT ;I/O interrupt type ;R114 dw 0000H ;active high & edge trigger ;R114;R86 db 0 ;source bus ID ;R114 db ISA_BUS_ID ;R86 ;R114 db 5 ;source bus IRQ ;R114 db IO_APIC_ID ;I/O apic id ;R114 db 5 ;destination I/O APIC INTIN# ;R114TOTAL_ENTRY = TOTAL_ENTRY + 1 ;R114IO_Int_Entry6: ;R114 db IOInt_Entry_ID ;I/O interrupt entry ID ;R114 db TYPE_INT ;I/O interrupt type ;R114 dw 0000H ;active high & edge trigger ;R114;R86 db 0 ;source bus ID ;R114 db ISA_BUS_ID ;R86 ;R114 db 6 ;source bus IRQ ;R114 db IO_APIC_ID ;I/O apic id ;R114 db 6 ;destination I/O APIC INTIN# ;R114TOTAL_ENTRY = TOTAL_ENTRY + 1 ;R114IO_Int_Entry7: ;R114 db IOInt_Entry_ID ;I/O interrupt entry ID ;R114 db TYPE_INT ;I/O interrupt type ;R114 dw 0000H ;active high & edge trigger ;R114;R86 db 0 ;source bus ID ;R114 db ISA_BUS_ID ;R86 ;R114 db 7 ;source bus IRQ ;R114 db IO_APIC_ID ;I/O apic id ;R114 db 7 ;destination I/O APIC INTIN# ;R114TOTAL_ENTRY = TOTAL_ENTRY + 1 ;R114IO_Int_Entry8: ;R114 db IOInt_Entry_ID ;I/O interrupt entry ID ;R114 db TYPE_INT ;I/O interrupt type ;R114 dw 0000H ;active high & edge trigger ;R114;R86 db 0 ;source bus ID ;R114 db ISA_BUS_ID ;R86 ;R114 db 8 ;source bus IRQ ;R114 db IO_APIC_ID ;I/O apic id ;R114 db 8 ;destination I/O APIC INTIN# ;R114TOTAL_ENTRY = TOTAL_ENTRY + 1 ;R114IO_Int_Entry9: ;R114 db IOInt_Entry_ID ;I/O interrupt entry ID ;R114 db TYPE_INT ;I/O interrupt type ;R114 dw 0000H ;active high & edge trigger ;R114;R86 db 0 ;source bus ID ;R114 db ISA_BUS_ID ;R86 ;R114 db 9 ;source bus IRQ ;R114 db IO_APIC_ID ;I/O apic id ;R114 db 9 ;destination I/O APIC INTIN# ;R114TOTAL_ENTRY = TOTAL_ENTRY + 1 ;R114IO_Int_Entry10: ;R114 db IOInt_Entry_ID ;I/O interrupt entry ID ;R114 db TYPE_INT ;I/O interrupt type ;R114 dw 0000H ;active high & edge trigger ;R114;R86 db 0 ;source bus ID ;R114 db ISA_BUS_ID ;R86 ;R114 db 10 ;source bus IRQ ;R114 db IO_APIC_ID ;I/O apic id ;R114 db 10 ;destination I/O APIC INTIN# ;R114TOTAL_ENTRY = TOTAL_ENTRY + 1 ;R114IO_Int_Entry11: ;R114 db IOInt_Entry_ID ;I/O interrupt entry ID ;R114 db TYPE_INT ;I/O interrupt type ;R114 dw 0000H ;active high & edge trigger ;R114;R86 db 0 ;source bus ID ;R114 db ISA_BUS_ID ;R86 ;R114 db 11 ;source bus IRQ ;R114 db IO_APIC_ID ;I/O apic id ;R114 db 11 ;destination I/O APIC INTIN# ;R114TOTAL_ENTRY = TOTAL_ENTRY + 1 ;R114IO_Int_Entry12: ;R114 db IOInt_Entry_ID ;I/O interrupt entry ID ;R114 db TYPE_INT ;I/O interrupt type ;R114 dw 0000H ;active high & edge trigger ;R114;R86 db 0 ;source bus ID ;R114 db ISA_BUS_ID ;R86 ;R114 db 12 ;source bus IRQ ;R114 db IO_APIC_ID ;I/O apic id ;R114 db 12 ;destination I/O APIC INTIN# ;R114TOTAL_ENTRY = TOTAL_ENTRY + 1 ;R114IO_Int_Entry13: ;R114 db IOInt_Entry_ID ;I/O interrupt entry ID ;R114 db TYPE_INT ;I/O interrupt type ;R114 dw 0000H ;active high & edge trigger ;R114;R86 db 0 ;source bus ID ;R114 db ISA_BUS_ID ;R86 ;R114 db 13 ;source bus IRQ ;R114 db IO_APIC_ID ;I/O apic id ;R114 db 13 ;destination I/O APIC INTIN# ;R114TOTAL_ENTRY = TOTAL_ENTRY + 1 ;R114IO_Int_Entry14: ;R114 db IOInt_Entry_ID ;I/O interrupt entry ID ;R114 db TYPE_INT ;I/O interrupt type ;R114 dw 0000H ;active high & edge trigger ;R114;R86 db 0 ;source bus ID ;R114 db ISA_BUS_ID ;R86 ;R114 db 14 ;source bus IRQ ;R114 db IO_APIC_ID ;I/O apic id ;R114 db 14 ;destination I/O APIC INTIN# ;R114TOTAL_ENTRY = TOTAL_ENTRY + 1 ;R114IO_Int_Entry15: ;R114 db IOInt_Entry_ID ;I/O interrupt entry ID ;R114 db TYPE_INT ;I/O interrupt type ;R114 dw 0000H ;active high & edge trigger ;R114;R86 db 0 ;source bus ID ;R114 db ISA_BUS_ID ;R86 ;R114 db 15 ;source bus IRQ ;R114 db IO_APIC_ID ;I/O apic id ;R114 db 15 ;destination I/O APIC INTIN# ;R114TOTAL_ENTRY = TOTAL_ENTRY + 1 ;R114 ;R114 ;R114;R64 - start ;R114ifdef NEW_INTEL_IOAPIC ;R114;Interrupt entry for PCI IRQ routing ;R114 public IO_Int_Entry16 ;R114 public IO_Int_Entry17 ;R114 public IO_Int_Entry18 ;R114 public IO_Int_Entry19 ;R114IO_Int_Entry16: ;PIRQ A ;R114 db IOInt_Entry_ID ;I/O interrupt entry ID ;R114 db TYPE_INT ;I/O interrupt type ;R114 dw 000FH ;active low & level trigger ;R114;R86 db 1 ;source bus ID ;R114 db PCI_BUS_ID ;R86 ;R114 db (SLOT1_ID SHL 2)+0 ;source bus IRQ,PIRQ 0 ;R114 db IO_APIC_ID ;destination I/O APIC ID ;R114 db 16 ;destination I/O APIC INTIN# ;R114TOTAL_ENTRY = TOTAL_ENTRY + 1 ;R114 ;R114IO_Int_Entry17: ;PIRQ B ;R114 db IOInt_Entry_ID ;I/O interrupt entry ID ;R114 db TYPE_INT ;I/O interrupt type ;R114 dw 000FH ;active low & level trigger ;R114;R86 db 1 ;source bus ID ;R114 db PCI_BUS_ID ;R86 ;R114 db (SLOT2_ID SHL 2)+0 ;source bus IRQ,PIRQ 1 ;R114 db IO_APIC_ID ;destination I/O APIC ID ;R114 db 17 ;destination I/O APIC INTIN# ;R114TOTAL_ENTRY = TOTAL_ENTRY + 1 ;R114 ;R114IO_Int_Entry18: ;PIRQ C ;R114 db IOInt_Entry_ID ;I/O interrupt entry ID ;R114 db TYPE_INT ;I/O interrupt type ;R114 dw 000FH ;active low & level trigger ;R114;R86 db 1 ;source bus ID ;R114 db PCI_BUS_ID ;R86 ;R114 db (SLOT3_ID SHL 2)+0 ;source bus IRQ,PIRQ 2 ;R114 db IO_APIC_ID ;destination I/O APIC ID ;R114 db 18 ;destination I/O APIC INTIN# ;R114TOTAL_ENTRY = TOTAL_ENTRY + 1 ;R114 ;R114IO_Int_Entry19: ;PIRQ D ;R114 db IOInt_Entry_ID ;I/O interrupt entry ID ;R114 db TYPE_INT ;I/O interrupt type ;R114 dw 000FH ;active low & level trigger ;R114;R86 db 1 ;source bus ID ;R114 db PCI_BUS_ID ;R86 ;R114ifdef ONBOARD_SCSI_SLOT ;R114 db (ONBOARD_SCSI_SLOT SHL 2)+0 ;source bus IRQ,PIRQ 3 ;R114else; ONBOARD_SCSI_SLOT ;R114 db (SLOT4_ID SHL 2)+0 ;source bus IRQ,PIRQ 3 ;R114endif; ONBOARD_SCSI_SLOT ;R114 db IO_APIC_ID ;destination I/O APIC ID ;R114 db 19 ;destination I/O APIC INTIN# ;R114TOTAL_ENTRY = TOTAL_ENTRY + 1 ;R114 ;R114;R106 - start ;R114ifdef TEMP_PATCH_MP_FOR_5SLOT ;R114ifndef NO_USB_SUPPORT ;R114 db IOInt_Entry_ID ;I/O interrupt entry ID ;R114 db TYPE_INT ;I/O interrupt type ;R114 dw 000FH ;active low & level trigger ;R114 db PCI_BUS_ID ;R114 db (PIIX_ID SHR 1)+0 ;source bus IRQ,PIRQ 3 ;R114 db IO_APIC_ID ;destination I/O APIC ID ;R114 db 19 ;destination I/O APIC INTIN# ;R114TOTAL_ENTRY = TOTAL_ENTRY + 1 ;R114endif; NO_USB_SUPPORT ;R114 ;R114ifdef FIVE_PCI_SLOTS ;R114 db IOInt_Entry_ID ;I/O interrupt entry ID ;R114 db TYPE_INT ;I/O interrupt type ;R114 dw 000FH ;active low & level trigger ;R114 db PCI_BUS_ID ;R114 db (SLOT5_ID SHL 2)+0 ;source bus IRQ,PIRQ 0 ;R114 db IO_APIC_ID ;destination I/O APIC ID ;R114 db SLOT5_INTA+15 ;destination I/O APIC INTIN# ;R114TOTAL_ENTRY = TOTAL_ENTRY + 1 ;R114endif; FIVE_PCI_SLOTS ;R114endif; TEMP_PATCH_MP_FOR_5SLOT ;R114;R106 - end ;R114 ;R114;R73;Interrupt entry for motherboard IRQ routing ;R114;R73 ;R114;R73IO_Int_Entry20: ;MIRQ 0 ;R114;R73 db IOInt_Entry_ID ;I/O interrupt entry ID ;R114;R73 db TYPE_INT ;I/O interrupt type ;R114;R73 dw 0000H ;active low & level trigger ;R114;R73 db 0 ;source bus ID ;R114;R73 db 0 ;source bus IRQ ;R114;R73 db IO_APIC_ID ;destination I/O APIC ID ;R114;R73 db 20 ;destination I/O APIC INTIN# ;R114;R73TOTAL_ENTRY = TOTAL_ENTRY + 1 ;R114;R73 ;R114;R73;reserved Interrupt entry ;R114;R73IO_Int_Entry21: ;dummy ;R114;R73 db IOInt_Entry_ID ;I/O interrupt entry ID ;R114;R73 db TYPE_INT ;I/O interrupt type ;R114;R73 dw 0000H ;active low & level trigger ;R114;R73 db 0 ;source bus ID ;R114;R73 db 0 ;source bus IRQ ;R114;R73 db IO_APIC_ID ;destination I/O APIC ID ;R114;R73 db 21 ;destination I/O APIC INTIN# ;R114;R73TOTAL_ENTRY = TOTAL_ENTRY + 1 ;R114;R73 ;R114;R73;reserved Interrupt entry ;R114;R73IO_Int_Entry22: ;spare ;R114;R73 db IOInt_Entry_ID ;I/O interrupt entry ID ;R114;R73 db TYPE_INT ;I/O interrupt type ;R114;R73 dw 0000H ;active low & level trigger ;R114;R73 db 0 ;source bus ID ;R114;R73 db 0 ;source bus IRQ ;R114;R73 db IO_APIC_ID ;destination I/O APIC ID ;R114;R73 db 22 ;destination I/O APIC INTIN# ;R114;R73TOTAL_ENTRY = TOTAL_ENTRY + 1 ;R114 ;R114IO_Int_Entry23: ;for SMI ;R114 db IOInt_Entry_ID ;I/O interrupt entry ID ;R114 db TYPE_SMI ;I/O interrupt type ;R114 dw 0000H ;active low & level trigger ;R114;R86 db 0 ;source bus ID ;R114 db ISA_BUS_ID ;R86 ;R114 db 0 ;source bus IRQ ;R114 db IO_APIC_ID ;destination I/O APIC ID ;R114 db 23 ;destination I/O APIC INTIN# ;R114TOTAL_ENTRY = TOTAL_ENTRY + 1 ;R114 ;R114;Interrupt entry for local APIC ;R114 ;R114LOCAL_INT_ENTRY_ID EQU 04H ;R114Local_Int_Entry1: ;R114 db LOCAL_INT_ENTRY_ID ;local interrupt entry ID ;R114 db TYPE_EXTINT ;interrupt type ;R114;R86 dw 0005H ;active high & edge trigger ;R114;R86 db 0 ;source bus ID ;R114 dw 0 ;R86 ;R114 db PCI_BUS_ID ;R86 ;R114 db 0 ;source bus IRQ ;R114 db 0FFH ;destination LOCAL APIC ID ;R114 db 0 ;destination LOCAL APIC INTIN# ;R114TOTAL_ENTRY = TOTAL_ENTRY + 1 ;R114 ;R114Local_Int_Entry2: ;R114 db LOCAL_INT_ENTRY_ID ;local interrupt entry ID ;R114 db TYPE_NMI ;interrupt type ;R114;R86 dw 0005H ;active high & edge trigger ;R114;R86 db 0 ;source bus ID ;R114 dw 0 ;R86 ;R114 db PCI_BUS_ID ;R86 ;R114 db 0 ;source bus IRQ ;R114 db 0FFH ;destination I/O APIC ID ;R114 db 1 ;destination I/O APIC INTIN# ;R114TOTAL_ENTRY = TOTAL_ENTRY + 1 ;R114 ;R114endif; NEW_INTEL_IOAPIC ;R114;R64 - end ;R114 ;R114;LOCAL_INT_ENTRY_ID EQU 04H ;R114;Local_Int_Entry1: ;R114; db LOCAL_INT_ENTRY_ID ;local interrupt entry ID ;R114; db TYPE_EXTINT ;interrupt type ;R114; dw 0005H ;active high & edge trigger ;R114; db 0 ;source bus ID ;R114; db 2 ;source bus IRQ ;R114; db 0FFH ;destination LOCAL APIC ID ;R114; db 0 ;destination LOCAL APIC INTIN# ;R114;TOTAL_ENTRY = TOTAL_ENTRY + 1 ;R114; ;R114;Local_Int_Entry2: ;R114; db LOCAL_INT_ENTRY_ID ;local interrupt entry ID ;R114; db TYPE_NMI ;interrupt type ;R114; dw 0005H ;active high & edge trigger ;R114; db 0 ;source bus ID ;R114; db 2 ;source bus IRQ ;R114; db 0FFH ;destination I/O APIC ID ;R114; db 1 ;destination I/O APIC INTIN# ;R114;TOTAL_ENTRY = TOTAL_ENTRY + 1 ;R114 ;R114TOTAL_TABLE_ENTRY EQU TOTAL_ENTRY ;R114MPCFG_LEN EQU $ - offset MP_Config_Table ;R114TOTALMPCFG_LEN EQU $ - offset MP_FP_Stru ;R104 - starts Public P1_Upd_Ver P1_Upd_Ver Label Byte db 0FFh Public P2_Upd_Ver P2_Upd_Ver Label Byte db 0FFh ;R104 - ends ;R114 start public P1_SiGn public P2_SiGn P1_SiGn: dd 0 P2_SiGn: dd 0 ;R114 end endif; MP_SUPPORT ;R59 - end ;R65 - start ;R140 ifdef Notebook_Power_Management if STD_Function EQ 1 ;R140 ;R139 Public ZV_Resume_Byte ;R139 ZV_Resume_Byte EQU 1Dh Public Check_0V_Resume Check_0V_Resume Proc Near ;R139 - start ifdef ACPI_SUPPORT ifdef S4_SUPPORT Call Check_S4_Resume jz short @F ret @@: endif ;S4_SUPPORT endif ;ACPI_SUPPORT ;R139 - end pusha mov al,0fh NMI_OFF call Get_Cmos ;R65A xor ah,ah cmp al,ZV_Resume_Byte ;R65A jne short @F je short @F ;R65A xor al,al @@: or al,al popa ret Check_0V_Resume Endp ;R139 - start ifdef ACPI_SUPPORT ifdef S4_SUPPORT Public Check_S4_Resume Check_S4_Resume Proc Near pusha mov al,0fh NMI_OFF call Get_Cmos cmp al,S4_Resume_Byte je short @F xor al,al @@: or al,al popa ret Check_S4_Resume Endp endif ;S4_SUPPORT endif ;ACPI_SUPPORT ;R139 - end endif ;STD_Function EQ 1 ;R140 ;R140 endif ;Notebook_Power_Management ;R65 - end ;R94 - start ifdef E000_SMI_SUPPORT Public Intel_PMI_Ret Intel_PMI_Ret: pop ebx Call Restore_E000_Shadow_Status db 0FH,0AAH ;RSM endif ;E000_SMI_SUPPORT ;R94 - end ;R67 - start ;Function : Issue whole system reset to clear PCI master devices status for ; next boot. Note : this reset function is the same cold start, ; BIOS need to save flag for warm booting. We use PCI register ; I/O port 0CF9H to issue reset signal. Some chipsets didn't ; implement this port. ;Input : none ;Output: none ifdef Specail_align_for_Memphis98 ;R124 align 16 ;R124 endif; Specail_align_for_Memphis98 ;R124 public Issue_System_Reset Issue_System_Reset proc near ifdef PCI_RESET_SUPPORT ;R69 mov al,0fh NMI_OFF ;get shutdown info. ;R69 call Get_Cmos ;R155 mov al,0FH NMI_OFF ;get shutdown info. ;R69 ;R155 out CMOS,al ;R69 ;R155 newiodelay ;R69 ;R155 in al,CMOS+1 ;R69 ;R155 newiodelay ;R69 ;R155 ;R155 or al,al ;warm reset or exit from setup ;R155 jnz short ShutDown_Func ;R69 push ax ;R69 mov dx,0cf9h ;I/O port 0cf9H ;R69 in al,dx ;R69 test al,02H ;CPU reseted ? ;R69 jnz short Already_Reseted ;R69 push ax mov ax,G_RAM mov es,ax assume es:G_RAM cmp es:USER_REBOOT,CTRL_ALT_DEL jne short Not_Warm_Boot ;save warm boot flag in CMOS for POST usage ifndef No_Save_Warm_Boot_Flag ;R148 mov al,0FH NMI_OFF out CMOS,al newiodelay mov al,0AAH ;warm boot mark out CMOS+1 ,al newiodelay endif ;No_Save_Warm_Boot_Flag ;R148 Not_Warm_Boot: ifdef ZIDA_SPECIAL_ISSUE_SYSTEM_RESET ;R160 extrn Ct_Issue_System_Reset:Near ;R160 call Ct_Issue_System_Reset ;R160 endif; ZIDA_SPECIAL_ISSUE_SYSTEM_RESET ;R160 ;R128 - start ;Turn off display (for some VGA use SGRAM) mov dx,3c4h mov al,01h out dx,al inc dl ;dx=3c5h in al,dx ;read current value;R128A or al,20h ;disable display out dx,al ;R128 - end ;R69 pop ax ;R69 or al,06H ;reset CPU & chipset ;R121 ;R112 - start ;R121 ifdef ALiM153x_Hardware_RESET ;R121 mov eax,80001044H ;index port ;R121 mov dx,0cf8H ;R121 out dx,eax ;R121 NEWIODELAY ;R121 mov dl,0fcH ;R121 mov al,80h ;R121 out dx,al ;R121 NEWIODELAY ;R121 mov al,0feh ;R121 out 64h,al ;R121 jmp $ ;R121 endif ;ALiM153x_Hardware_RESET ;R121 ;R112 - end ;R121 ;R121 ;R71 - start ;R121 ifdef LYNX_PCI_RESET ;R121 mov eax,80000060H ;index port ;R121 mov dx,0cf8H ;R121 out dx,eax ;R121 NEWIODELAY ;R121 mov dl,0ffH ;register 63H bit 0 to reset ;R121 in al,dx ;R121 NEWIODELAY ;R121 or al,01H ;enable system reset ;R121 out dx,al ;R121 ;R71 - end ;R121 else; LYNX_PCI_RESET ;R71 ;R121 ifdef VIA_PCI_RESET ;R102 - starts ;R121 ;R102A ifndef VT586_ACPI ;R102A ;R121 ifdef VT586_ACPI ;R102B ;R121 mov eax,80000000H + VT586_ACPI + 40h ;R102B ;R121 mov dx,0cf8H ;R102B ;R121 out dx,eax ;R102B ;R121 NEWIODELAY ;R102B ;R121 mov dl,0fdH ;R102B Register 41h Bit 7 ;R121 in al,dx ;R102B ;R121 NEWIODELAY ;R102B ;R121 and al,not 80H ;R102B Clear Bit 7 ;R121 out dx,al ;R102B ;R121 endif; VT586_ACPI ;R102B ;R121 mov eax,80003808H ;R102C index port ;R121 mov dx,0cf8H ;R102C ;R121 out dx,eax ;R102C ;R121 NEWIODELAY ;R102C ;R121 mov dl,0fcH ;R102C register 08H = Revision ;R121 in al,dx ;R102C ;R121 cmp al,22h ;R102C ;R121 jb @f ;R102C ;R121 ;R121 mov eax,80003844H ;index port ;R121 mov dx,0cf8H ;R121 out dx,eax ;R121 NEWIODELAY ;R121 mov dl,0ffH ;register 47H bit 0 to reset ;R121 in al,dx ;R121 NEWIODELAY ;R121 or al,01H ;enable system reset ;R121 out dx,al ;R121 @@: ;R102C ;R121 ;R102B endif; VT586_ACPI ;R102A ;R121 else ;VIA_PCI_RESET ;R102 - ends ;R121 mov dx,0cf9h ;R69 ;R121 ;R91A mov al,04H ;enable system reset ;R91 ;R121 ;R91A out dx,al ;R91 ;R121 ;R91A NEWIODELAY ;R91 ;R121 mov al,06H ;issue reset ;R69 ;R121 out dx,al ;R121 endif ;VIA_PCI_RESET ;R102 ;R121 endif; LYNX_PCI_RESET ;R71 ;R121 - start ;R132 - starts ifdef SPECIAL_ISSUE_SYSTEM_RESET ifndef ZIDA_SPECIAL_ISSUE_SYSTEM_RESET ;R160 extrn Ct_Issue_System_Reset:Near call Ct_Issue_System_Reset endif; ZIDA_SPECIAL_ISSUE_SYSTEM_RESET ;R160 endif ;SPECIAL_ISSUE_SYSTEM_RESET ;R132 - ends ifdef ALiM153x_Hardware_RESET ;R134A mov eax,80001044H ;index port mov eax,80000000h + M1543 + 44h ;R134A mov dx,0cf8H out dx,eax NEWIODELAY mov dl,0fcH mov al,80h out dx,al NEWIODELAY mov al,0feh out 64h,al jmp $ endif ;ALiM153x_Hardware_RESET ifdef LYNX_PCI_RESET mov eax,80000060H ;index port mov dx,0cf8H out dx,eax NEWIODELAY mov dl,0ffH ;register 63H bit 0 to reset in al,dx NEWIODELAY or al,01H ;enable system reset out dx,al endif; LYNX_PCI_RESET ifdef VIA_PCI_RESET ifndef No_Cut_IRQ12_When_No_PS2_Pluged ;R121H Disable_VIA_PS2_In_PCI_RESET EQU 1 ;R121H endif; No_Cut_IRQ12_When_No_PS2_Pluged ;R121H IFDEF Disable_VIA_PS2_In_PCI_RESET ;R121G - start mov eax,80000000H + VT586 + 058h ;Release IRQ12 mov dx,0cf8H out dx,eax NEWIODELAY mov dl,0feH ;Register 5Ah Bit 1 in al,dx NEWIODELAY and al,not 02H ;Clear Bit 1 out dx,al ENDIF; Disable_VIA_PS2_In_PCI_RESET ;R121G - end ifdef VT586_ACPI mov eax,80000000H + VT586_ACPI + 40h mov dx,0cf8H out dx,eax NEWIODELAY mov dl,0fdH ;Register 41h Bit 7 in al,dx NEWIODELAY and al,not 80H ;Clear Bit 7 out dx,al endif; VT586_ACPI ;R121E mov eax,80003808H ;index port ifndef VT596 ;R121F mov eax,80000000H + VT586 + 08h ;R121E index port mov dx,0cf8H out dx,eax NEWIODELAY mov dl,0fcH ;register 08H = Revision in al,dx cmp al,22h jb @f endif; VT596 ;R121F ;R121E mov eax,80003844H ;index port mov eax,80000000H + VT586 + 44h ;R121E index port mov dx,0cf8H out dx,eax NEWIODELAY mov dl,0ffH ;register 47H bit 0 to reset in al,dx NEWIODELAY or al,01H ;enable system reset out dx,al jmp $ ;R121E @@: endif ;VIA_PCI_RESET ifdef SIS_5598_PCI_RESET mov dx,0cf9h mov al,0ch ;issue CPU reset out dx,al jmp short $ ;R121D ;R121D xor cx,cx ;R121A ;R121D loop $ ;R121A ;R121D xor cx,cx ;R121B ;R121D loop $ ;R121B ;R121D xor cx,cx ;R121C ;R121D loop $ ;R121C ;R121D xor cx,cx ;R121C ;R121D loop $ ;R121C endif; SIS_5598_PCI_RESET ;R126 - start ;R126B ifdef SIS_5591_PCI_RESET ifdef SIS_5595_PCI_RESET ;R126B mov eax,80000860H ;index port mov dx,0cf8H out dx,eax NEWIODELAY mov dx,0cffh in al, dx or al, 018h ;issue CPU reset out dx,al xor cx,cx loop $ jmp short $ ;R126A endif; SIS_5595_PCI_RESET ;R126B ;R126B endif; SIS_5591_PCI_RESET ;R126 - end ;R138 - start ifdef PCI_RESET_FOR_443BX mov eax,(80000000H + (TSC_ID SHL 8)+54H) mov dx,0CF8H out dx,eax NEWIODELAY NEWIODELAY mov dl,0FFH ;register 57H in al,dx NEWIODELAY NEWIODELAY and al,11111000b ;disable DRAM refresh out dx,al NEWIODELAY NEWIODELAY mov cx, 0640h ; Delay 110us for spec. @@: ; NEWIODELAY ; loop short @B ; ;R138A mov eax,(80000000H + (TSC_ID SHL 8)+54H) ;R138A mov dx,0CF8H ;R138A out dx,eax ;R138A NEWIODELAY ;R138A NEWIODELAY ;R138A mov dl,0FFH ;register 57H ;R138A in al,dx ;R138A NEWIODELAY ;R138A NEWIODELAY ;R138A or al,11111001b ;enable DRAM refresh(15.6us) ;R138A out dx,al ;R138A NEWIODELAY ;R138A NEWIODELAY endif; PCI_RESET_FOR_443BX ;R138 - end ;R146 - starts ifdef VSA_VGA ifdef Cx5530_PCI_RESET mov cx, (Cx5530_PCI_REG shl 8)+ 44h mov eax, 80000000h mov ax, cx and al, NOT 03h ;32 bit access for PCI mov dx, 0cf8h ;index is 0cf8h out dx, eax NEWIODELAY add dl, 4 ;start from 0cfch mov al, cl and al, 03h add dl, al ;byte index to read in al, dx NEWIODELAY or al,0fh out dx,al endif ;Cx5530_PCI_RESET ;R146A - starts ifdef Cx5540_PCI_RESET mov cx, (Cx5540_PCI_REG shl 8)+ 44h mov eax, 80000000h mov ax, cx and al, NOT 03h ;32 bit access for PCI mov dx, 0cf8h ;index is 0cf8h out dx, eax NEWIODELAY add dl, 4 ;start from 0cfch mov al, cl and al, 03h add dl, al ;byte index to read in al, dx NEWIODELAY or al,0fh out dx,al endif ;Cx5540_PCI_RESET ;R146A - ends endif ;VSA_VGA ;R146 - ends ;R142 - start ifdef Some_Delay_Before_PCIRESET ;R154 mov cx, 0640h ; Delay 110us for spec. xor cx,cx ;R154 @@: ; NEWIODELAY ; NEWIODELAY ;R154 loop short @B ; endif; Some_Delay_Before_PCIRESET ;R142 - end ;R149 - start ifdef PATCH_MII_JUMPLESS ;set warm boot flag for jumperless routine to identify which step ;is running. mov al,03AH NMI_OFF out CMOS,al newiodelay mov al,056H ;warm second boot out CMOS+1 ,al newiodelay endif; PATCH_MII_JUMPLESS ;R149 - end ;M01 - starts ifdef RPB_ENABLED ;if Preboot Agent is running issue a CPU only reset in order for ;internal modems to survive a reset. This may cause other modifications ;to the state of the chipset in order to survive a CPU only reset. ;These modifications can be put into rpbp_prepare_for_reset function ;in RPB_PORT.ASM extrn rpb_f000_is_running:near call rpb_f000_is_running jc do_reset ; NC if RPB is running mov dx,0cf9h mov al,04H ; cpu reset only out dx,al jmp Already_Reseted do_reset: endif ; RPB_ENABLED ;M01 - ends mov dx,0cf9h mov al,06H ;issue reset out dx,al ;R121 - end Already_Reseted: ;R69 out dx,al ;R69 pop ax ShutDown_Func: else ; PCI_RESET_SUPPORT ;R132A ifdef SPECIAL_ISSUE_SYSTEM_RESET ;R132A extrn Ct_Issue_System_Reset:Near ;R132A call Ct_Issue_System_Reset ;R132A endif ;SPECIAL_ISSUE_SYSTEM_RESET ;R132A endif; PCI_RESET_SUPPORT ret Issue_System_Reset endp ;R67 - end ifdef USB_SUPPORT ;R83 public USB_RAM_SEG ;R83 USB_RAM_SEG dw ? ;R83 public USB_STATUS ;R92 ;R147USB_STATUS db ? ;R92 USB_STATUS db 01h ;R147 endif ;USB_SUPPORT ;R83 ;R114;R85 - starts ;R114ifdef MP_SUPPORT ;R85A ;R114ifdef P6_BIOS_ONLY ;R85A ;R114Set_2nd_Local_APIC_ID: ;R114 call Enter_Prot_mode ;R114 mov dword ptr ds:[0fee00020h], 01000000h ;local APIC ID = 1 ;R114 call Back_Real_Mode ;R114 far_jmp , 0F000h ;R114endif ;P6_BIOS_ONLY ;R85A ;R114endif ;MP_SUPPORT ;R85A ;R114;R85 - ends ;R157 - start ;R157A - Update the MBI Structure from v1.0 to v1.01 as Gemlight request. ; --> Change the Major/Minor Version of MBI Structure to be ASCII ; format & change the size of Minor Version from 1 byte to 2 bytes. ; ; --------- Gemlight MBI Structure Data Area ---------- ; All below valuable/information is set in the correspondiong BIOS.CFG ; The reference example need to be defined in BIOS.CFG is as followings: ; ifdef Gemlight_MBI align 16 public Gemlight_MBI_Struc public MBIChecksum Gemlight_MBI_Struc: MBIHeader db 'MBI-ID' ; Identifier for Gemlight M/B MBIMajorVersion db Gemlight_Struc_MajorVer ; Major Version of Structure MBIMinorVersion dw Gemlight_Struc_MinorVer ; Minor Version of Structure MBIReserved_D1 db 7 dup (?) ; Reserved MBIGModelName db Gemlight_GModel ; 16 bytes long MBIDModelName db Gemlight_DModel ; 16 bytes long MBIModelVersion db Gemlight_Model_Ver ; Version number of this M/B MBIModelRevision db Gemlight_Model_Rev ; Revision number of this M/B MBI871DSupport db Gemlight_871D_Config ; 871D configuration byte MBIReserved_D2 db 12 dup (?) ; Reserved MBIChecksum db Gemlight_MBIChecksum ; Checksum of MBI structure IF (($ - Gemlight_MBI_Struc) NE 64) %OUT ERROR, Gemlight MBI Sturecture size must be 64 bytes. .ERR ENDIF endif ;Gemlight_MBI ;R157 - end FCODE ENDS END