; []==========================================================[] ; ; This source code is classified as confidential and ; contains trade secrets owned by Award Software, Inc. ; ; Copyright 1984, 1997 ; Award Software, Inc. ; All rights reserved. ; ; []==========================================================[] ;---------------------------------------------------------------------------- ;Rev Date Name Description ;---------------------------------------------------------------------------- ;R05 03/09/99 DNL Added RTC wake up from S4 support ;R04 02/25/99 RIC Report Sensor IO port for VIA686HM_Port definition. ;R03A 02/22/99 RIC Fixed that R13 code always define ACPI_Port/SMBus_Port ; to cause compiling fail in PMUPOST if BIOS.CFG no ; define ACPI_Port/SMBus_Port. ; (This is the issue of GETASL.EXE) ;R03 02/03/99 ADS Fixed NT5.0 Beta2 AGP display card can't be installed. ;R02B 12/01/98 RIC Re-modify the Reg offset of Throttling Duty Cycle. ; for HCT test more easy to pass Throttling Duty Cycle Test. ;R02A 11/26/98 RIC Re-modify the Reg Start & offset of Throttling Duty Cycle ; for HCT test fail in Throttling Duty Cycle ;R02 11/10/98 RIC Modify the Reg Start & offset of Throttling Duty Cycle ; for VT596 chip. ;R01 09/08/98 RIC Fix that Throtling function of HCT7.6 can't support. ;R00 08/15/98 RIC Initialization. ;---------------------------------------------------------------------------- ;FACP definition for the VIA south chip ; PMIOBase EQU ACPI_Port ;596 PM IO base value programmed in INT_MODEL EQU 0 ;Interrupt mode of ACPI description. SCI_INT EQU 09 ;System pin the SCI interrupt is wired to. SCI_EN EQU 1 ;Enable ACPI SCI PM1a_EVT_BLK EQU PMIOBase+0 ;IO of PM status register PM1b_EVT_BLK EQU 0 ;IO of PM status register PM1a_CNT_BLK EQU PMIOBase+4 ;IO of PM control register PM1b_CNT_BLK EQU 0 ;IO of PM control register PM2_CNT_BLK EQU 0 ;IO of PM control register PM_TMR_BLK EQU PMIOBase+08h ;IO of PM timer register GPE0_BLK EQU PMIOBase+20h ;IO of general purpose register GPE1_BLK EQU 0 ;IO of general purpose register PM1_EVT_LEN EQU 4 ;No. of byte of PM1?_EVT_BLK. PM1_CNT_LEN EQU 2 ;No. of byte of PM1?_CNT_BLK. PM2_CNT_LEN EQU 0 ;No. of byte of PM2_CNT_BLK. PM_TM_LEN EQU 4 ;No. of byte of PM_TMR_BLK. GPE0_BLK_LEN EQU 4 ;No. of byte of GPE0_BLK GPE1_BLK_LEN EQU 0 ;No. of byte of GPE1_BLK GPE1_BASE EQU 0 ; P_LVL2_LAT EQU 90 ;Worst case HW latency in microsec. to enter/exit C2 P_LVL3_LAT EQU 900 ;Worst case HW latency in microsec. to enter/exit C3 FLUSH_SIZE EQU 0 ; FLUSH_STRIDE EQU 0 ; ;R02 DUTY_OFFSET EQU 1 ;Offset in P_CLK register of CPU duty cycle setting ;R02A DUTY_OFFSET EQU 0 ;R02 Offset in P_CLK register of CPU duty cycle setting ;R02B DUTY_OFFSET EQU 3 ;R02A Offset in P_CLK register of CPU duty cycle setting ;R01 DUTY_WIDTH EQU 0 ;Width of CPU duty cycle bits in P_CLK register. ;R02 DUTY_WIDTH EQU 3 ;R01 Width of CPU duty cycle bits in P_CLK register. ;R02A DUTY_WIDTH EQU 4 ;R02 Width of CPU duty cycle bits in P_CLK register. DUTY_OFFSET EQU 0 ;R02B Offset in P_CLK register of CPU duty cycle setting DUTY_WIDTH EQU 1 ;R02A Width of CPU duty cycle bits in P_CLK register. S4BIOS_F EQU 01h ; Timer_32bit EQU 100h ; ACPI_Port_Mid EQU ACPI_Port+80h ; ;R03A IFNDEF ACPI_Port ;R03 ;R03A ACPI_Port EQU 0 ;R03 ;R03A ENDIF; ACPI_Port ;R03 ;R03A IFNDEF SMBus_Port ;R03 ;R03A SMBus_Port EQU 0 ;R03 ;R03A ENDIF; SMBus_Port ;R03 ;R03A IF ACPI_Port NE 0 ;R03 ;R03A END_IO2_Start EQU ACPI_Port+100h ;R03 answer NT5.0 that can be used ;R03A END_IO2_End EQU ACPI_Port+0FFFH ;R03 device IO. ;R03A ENDIF; ACPI_Port NE 0 ;R03 ;R03A IF SMBus_Port NE 0 ;R03 ;R03A END_IO3_Start EQU SMBus_Port+010h ;R03 ;R03A ENDIF; SMBus_Port NE 0 ;R03 ;R03A - satrts END_IO2_Start EQU (ACPI_Port+100h) ;R13 answer NT5.0 that can be used END_IO2_End EQU (ACPI_Port+0FFFH) ;R13 device IO. Hi_END_IO2_Len EQU 0FFFFh-END_IO2_Start ;R04 IFDEF SMBus_Port END_IO3_Start EQU (SMBus_Port+010h) END_IO3_End EQU (SMBus_Port+0FFFH) ;R04 Hi_END_IO3_Len EQU 0FFFFh-END_IO3_Start ;R04 ENDIF; SMBus_Port IFDEF VIA686HM_Port ;R04 END_IO4_Start EQU (VIA686HM_Port+080h) ;R04 Hi_END_IO4_Len EQU 0FFFFh-END_IO4_Start ;R04 ENDIF; VIA686HM_Port ;R04 ;R03A - ends ;R02A FACPFlag EQU (PROC_C1+WBINVDFlag+SLP_BUTTON+Timer_32bit) ;R05 FACPFlag EQU (PROC_C1+WBINVDFlag+SLP_BUTTON) ;R02A FACPFlag EQU (PROC_C1+WBINVDFlag+SLP_BUTTON+RTC_S4) ;R05 FACSFlag EQU S4BIOS_F SMI_CMD EQU PMIOBase+02fh ;SMI command port SMI_CMD_RD EQU PMIOBase+02fh ;SMI readm command port S2 EQU 02h ;value for S2 state S3 EQU 08h ;value for S3 state S4 EQU 00h ;value for S4 state DAY_ALRM EQU 7dh ;Index of RTC CMOS day alarm MON_ALRM EQU 7eh ;Index of RTC CMOS month alarm CENTURY_ALRM EQU 7fh ;Index of RTC CMOS year alarm GBL_CTL EQU PMIOBase+02ch ;Global Control ;These values are read from SMI_CMD ;by SMI handler to enable/disable ACPI. ACPI_ENABLE EQU 0A1h ;Value assigned by BIOS to check at software ;SMI handler to disable SMI and enable SCI. ACPI_DISABLE EQU 0A0h ;Value to enable SMI ownership ifdef S4_Support S4BIOS_REQ EQU 0A4h ;Value to enter S4 state (handle by BIOS) else; S4_Support S4BIOS_REQ EQU 00h ;Value to enter S4 state (handle by BIOS) ;0= Not support S4 state. ;0a4h= Support S4 sate. endif; S4_Support